Multi-state EEprom read and write circuits and techniques

  • US 5,172,338 A
  • Filed: 04/11/1990
  • Issued: 12/15/1992
  • Est. Priority Date: 04/13/1989
  • Status: Expired due to Term
First Claim
Patent Images

1. In an integrated circuit memory system having an array of a plurality of addressable semiconductor electrically erasable and programmable memory (EEprom) cells of the type having a source, a drain, a control gate, a floating gate capable of retaining a charge level programmed into it during use of the memory system, resulting in a definite memory state having a corresponding threshold of conduction relative to a set of predetermined threshold levels used to demarcate memory states, and an erase electrode capable of removing charge from said floating gate, said array of EEprom cells being organized into one or more sectors of cells, where cells in each sector are erasable simultaneously, and said memory system including a reading system for determining the programmed state of an addressed cell in a given sector, said reading system comprising:

  • a set of sector reference memory cells associated with each sector, each set of sector reference memory cells being made up of memory cells from the sector associated therewith, thereby being electrically erasable along with its associated sector, and each set being programmable and having the set of predetermined threshold duplicated therein;

    reprogramming means for duplicating the set of predetermined threshold to said set of sector reference memory cells after said set of sector reference memory cells has been erased along with its associated sector; and

    means for comparing the addressed cell'"'"'s programmed threshold relative to the set of predetermined thresholds duplicated in the set of sector reference memory cells associated with said given sector, thereby determining the memory state programmed in the addressed cell.

View all claims
    ×
    ×

    Thank you for your feedback

    ×
    ×