Methods of forming channels and vias in insulating layers

• US 5,173,442 A
• Filed: 03/24/1992
• Issued: 12/22/1992
• Est. Priority Date: 07/23/1990
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Microelectronics and Computer Technology Corporation
• Inventors: Carey, David H.
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): OJAN, OURMAZD
• Application Number:
  US07/857,011
• Time in Patent Office: 273 Days
• Field of Search: 437/187, 437/203, 437/225, 437/228, 437/229, 437/235, 437/238, 437/192, 437/194, 437/173
• US Class Current: 216/18
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 21/76804 by forming tapered via holes
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76808 involving intermediate temporary filling with material
• CPC Class Codes: H01L 21/76811 involving multiple stacked pre-patterned masks
• CPC Class Codes: H01L 21/76813 involving a partial via etch
• CPC Class Codes: H01L 21/76817 using printing or stamping techniques
• CPC Class Codes: H01L 2221/1031 Dual damascene by forming vias in the via-level dielectric prior to deposition of the trench-level dielectric
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H05K 2201/0166 Polymeric layer used for special processing, e.g. resist for etching insulating material or photoresist used as a mask during plasma etching
• CPC Class Codes: H05K 2201/09563 Metal filled via plated through-hole filled with insulating material H05K2201/0959
• CPC Class Codes: H05K 2203/0108 Male die used for patterning, punching or transferring
• CPC Class Codes: H05K 2203/025 Abrading, e.g. grinding or sand blasting deburring, rounding, bevelling or smoothing conductor edges H05K2203/0346
• CPC Class Codes: H05K 2203/0554 Metal used as mask for etching vias, e.g. by laser ablation
• CPC Class Codes: H05K 2203/0574 Stacked resist layers used for different processes
• CPC Class Codes: H05K 2203/107 : Using laser light shaping a substrate by laser ablation H05K3/0026
• CPC Class Codes: H05K 2203/1189 : Pressing leads, bumps or a die through an insulating layer
• CPC Class Codes: H05K 3/0023 : by exposure and development of a photosensitive insulating layer
• CPC Class Codes: H05K 3/0032 : of organic insulating material
• CPC Class Codes: H05K 3/0035 : of blind holes, i.e. having a metal layer at the bottom
• CPC Class Codes: H05K 3/0041 : by plasma etching
• CPC Class Codes: H05K 3/005 : Punching of holes
• CPC Class Codes: H05K 3/107 : by filling grooves in the support with conductive material H05K3/045, H05K3/101, H05K3/1258 and H05K3/465 take precedence
• CPC Class Codes: H05K 3/388 : by the use of a metallic or inorganic thin film adhesion layer
• CPC Class Codes: H05K 3/4076 : by thin-film techniques
• CPC Class Codes: H05K 3/422 : characterised by electroless plating method; pretreatment therefor
• CPC Class Codes: H05K 3/4644 : by building the multilayer layer by layer, i.e. build-up multilayer circuits making via holes in the insulating layers H05K3/0011; special circuit boards as base or core whereon the multilayer is built H05K3/4602
• CPC Class Codes: H05K 3/4661 : Adding a circuit layer by direct wet plating, e.g. electroless plating; insulating materials adapted therefor other insulating materials H05K3/387
• CPC Class Codes: Y10S 438/94 : Laser ablative material removal

Abstract

Channels extending partially through and vias extending completely through an insulating layer in an electrical interconnect such as a substrate or integrated circuit can be formed in a relatively few steps with low cost etching and patterning techniques. The channels and vias can then be filled with an electrical conductor in a relatively few steps. In one embodiment a non-erodible hard mask exposing the vias and channels is placed over a polyimide layer, an erodible soft mask exposing the vias but covering the channels is placed over the hard mask, and a plasma etch is applied. The via regions are etched until the soft mask completely erodes and then both the via and channel regions are etched to provide partially etched channels and fully etched vias. Thereafter a seed layer is deposited over the interconnect, and an electrically conductive layer is electrolytically deposited over the seed layer substantially filling the channels and vias. The interconnect surface is then planarized by polishing until the electrical conductor remains only in the channels and vias.

Claims

1. A method for forming a channel and a via in an insulating layer, said channel being a horizontally disposed in the top surface of and partially through the thickness of the insulating layer and said via being adjacent to the channel and vertically disposed and completely through the thickness of the insulating layer, said method comprising the steps of:

covering the insulating layer with a hard mask having an opening to expose the channel and the via wherein the hard mask is non-erodible by an etch;

covering the hard mask with a soft mask having an opening to expose the via but covering the channel wherein the soft mask is erodible by the etch;

applying the etch to at least partially remove the insulating layer where the via is exposed until the soft mask is eroded;

applying the etch after the soft mask is eroded to remove the insulating layer where the channel is exposed and to remove any of the insulating layer remaining where the via is exposed so that the channel and the via are formed; and

removing the hard mask from the insulating layer.

2. A method of forming a channel and a via in an insulating layer, said channel being a horizontally disposed in the top surface of and partially through the thickness of the insulating layer and said via being adjacent to the channel and vertically disposed and completely through the thickness of the insulating layer, said method comprising the steps of:

covering the insulating layer with a lower soft mask having an opening to expose the channel and the via wherein the lower soft mask is erodible by an etch;

covering the lower soft mask with an upper soft mask having an opening to expose the via but covering the channel wherein the upper soft mask is erodible by the etch;

applying the etch to at least partially remove the insulating layer where the via is exposed until the upper soft mask is eroded; and

applying the etch after the upper soft mask is eroded to remove the insulating layer where the channel is exposed and to remove any of the insulating layer remaining where the via is exposed so that the channel and the via are formed.

3. A method of forming a channel and a via in an insulating layer, said channel being a horizontally disposed in the top surface of and partially through the thickness of the insulating layer and said via being adjacent to the channel and vertically disposed and completely through the thickness of the insulating layer, said method comprising the steps of:

covering the insulating layer with a first soft mask having an opening to expose the via but covering the channel wherein the first soft mask is erodible by a first etch;

applying the first etch to at least partially remove the insulating layer where the vis is exposed;

covering the insulating layer with a second soft mask having an opening to expose the channel and the via wherein the second soft mask is erodible by a second etch; and

applying the second etch to remove the insulating layer where the channel is exposed and to remove any of the insulating layer remaining where the via is exposed so that the channel and the via are formed.

4. A method of forming a channel and a via in an insulating layer, said channel being a horizontally disposed in the top surface of and partially through the thickness of the insulating layer and said via being adjacent to the channel and vertically disposed and completely through the thickness of the insulating layer, said method comprising the steps of:

stamping the insulating layer with a patterned plate comprising a channel abutment and a via abutment extending from a plate surface so that the plate surface contacts the insulating layer, the channel abutment forms a channel indentation and the via abutment forms a via indentation deeper than the channel indentation in the insulating layer;

retracting the plate from the insulating layer; and

applying an etch to the insulating layer to remove residual material from the insulating layer beneath the via indentation so that the channel and the via are formed.

5. A method of forming a channel and a via in an insulating layer, said channel being a horizontally disposed in the top surface of and partially through the thickness of the insulating layer and said via being adjacent to the channel and vertically disposed and completely through the thickness of the insulating layer, said method comprising the steps of:

providing a layer of a first photoimagible insulator having a thickness that defines the distance from the bottom the channel to the bottom of the insulating layer;

providing a first mask which defines the via over the first photoimagible insulator;

directing a light source through the first mask at the first photoimagible insulator to alter the solubility of the exposed regions of the first photoimagible insulator;

removing the first photoimagible insulator in the via;

providing a layer of a second photoimagible insulator having a thickness that defines the depth of the channel over the first photoimagible insulator;

providing a second mask which defines the channel and the via over the second photoimagible insulator;

directing a light source through the second mask at the second photoimagible insulator to alter the solubility of the exposed regions of the second photoimagible insulator; and

removing the second photoimagible insulator in the channel and the via so that the channel and the via are formed.

6. A method of forming a channel and a via in an insulating layer, said channel being a horizontally disposed in the top surface of and partially through the thickness of the insulating layer and said via being adjacent to the channel and vertically disposed and completely through the thickness of the insulating layer, said method comprising the steps of:

covering the insulating layer with a mask having an opening to expose the channel and the via;

applying an etch to remove the insulating layer where the channel is exposed until the channel is formed and where the via is exposed until the via is partially formed through the thickness of the insulating layer; and

directing a laser beam at the partially formed via to remove the insulating layer remaining in the via so that the channel and the via are formed.

7. A method of forming a channel and a via containing an electrical conductor in an insulating layer, said channel being a horizontally disposed in the top surface of and partially through the thickness of the insulating layer and said via being adjacent to the channel and vertically disposed and completely through the thickness of the insulating layer, said method comprising the steps of:

covering the insulating layer with a first soft mask having an opening to expose the via and channel wherein the first soft mask is erodible by a first etch;

applying the first etch to remove the insulating layer where the channel is exposed and to partially remove the insulating layer where the via is exposed;

covering the insulating layer with a second soft mask having an opening to expose the via but covering the channel wherein the second soft mask is erodible by a second etch;

applying the second etch to remove the insulating layer remaining where the via is exposed so that the channel and the via are formed;

depositing a seed layer over the insulating layer and into the channel and the via; and

depositing an electrical conductor over the seed layer and into the channel and the via so that the electrical conductor substantially fills the channel and the via.

8. A method of forming a channel and a via in an insulating layer, said channel being a horizontally disposed in the top surface of and partially through the thickness of the insulating layer and said via being adjacent to the channel and vertically disposed and completely through the thickness of the insulating layer, said method comprising the steps of:

covering the insulating layer with a first soft mask having an opening to expose the via and channel wherein the first soft mask is erodible by a first etch;

applying the first etch to remove the insulating layer where the channel is exposed and to partially remove the insulating layer where the via is exposed;

covering the insulating layer with a second soft mask having an opening to expose the via but covering the channel wherein the second soft mask is erodible by a second etch;

applying the second etch to remove the insulating layer remaining where the via is exposed so that the channel and the via are formed;

depositing a first electrical conductor into the via so that the first electrical conductor fills the via substantially to the height of the bottom of the channel;

depositing a seed layer over the insulating layer and onto the first electrical conductor and the channel; and

depositing a second electrical conductor over the seed layer so that the channel and the via are substantially filled with electrical conductors.