Direct sequence spread spectrum communication system with self-synchronizing correlator and method

• US 5,179,570 A
• Filed: 07/19/1991
• Issued: 01/12/1993
• Est. Priority Date: 07/19/1991
• Status: Expired due to Fees

• Current Assignee: Physiometrix, Inc. (Pfizer Inc.)
• Original Assignee: Mir A. Imran
• Inventors: Imran, Mir A.
• Primary Examiner(s): Swann, Tod R.
• Application Number:
  US07/732,655
• Time in Patent Office: 543 Days
• Field of Search: 380/34, 380/48, 380/50, 375/1
• US Class Current: 375/142
• CPC Class Codes: H04B 1/70751 using partial detection H04B1/70758 takes precedence
• CPC Class Codes: H04B 1/709 Correlator structure

Abstract

Spread spectrum communication system comprising a transmitter for transmitting data in bit form from one location to a remote location. An encoder is provided for encoding the data with a chip sequence at a predetermined clock rate to provide encoded data which is transmitted to the remote location. A receiver is provided at the remote location for receiving the encoded data. The receiver includes a correlator having a shift register for storing a chip sequence on the encoded data in bit form at least three sequential times. A decoder is provided for polling the shift register during the three sequential times of the stored chip sequence in bit form at a clock rate of at least three times that of the clock rate of the chip sequence to ascertain whether a majority of the corresponding chips of the chip sequence stored in the shift register at the at least three sequential times are the same to provide an output. A comparator is provided for comparing the output with the corresponding chip of the transmitted chip sequence to ascertain whether they are the same and with an inverted chip corresponding to the chip of the transmitted chip sequence to ascertain whether they are the same to provide compared data. A summer is provided for summing the compared data to provide summed data, and an adjustable threshold is provided for determining when the summed data constitutes a valid data bit.

Claims

1. In a spread spectrum system, a transmitter for transmitting data in bit form from one location to a remote location, means for encoding the data with a chip sequence at a predetermined clock rate to provide encoded data which is transmitted to the remote location, a receiver at the remote location for receiving the encoded data, said receiver including a correlator which includes means for storing a chip sequence on the encoded data in bit form at least three sequential times, means for polling the means for storing a chip sequence during the three sequential times of the stored chip sequence in bit form at a clock rate of at least three times that of the clock rate of the chip sequence to ascertain whether the majority of the corresponding chips of the chip sequence stored in the means for storing from the at least three sequential times are the same to provide an output, means for comparing the output with the corresponding chip of the transmitted chip sequence to ascertain whether they are the same and with an inverted chip corresponding to the chip of the transmitted chip sequence to ascertain whether they are the same to provide compared data, means for summing the compared data to provide summed data and adjustable threshold means for determining when the summed data constitutes a valid data bit.

2. In a spread spectrum system, a transmitter for transmitting data in bit form from one location to a remote location, means for encoding the data with a chip sequence at a predetermined clock rate to provide encoded data which is transmitted to the remote location, a receiver at the remote location for receiving the encoded data, said receiver including a correlator which includes means for storing a chip sequence on the encoded data in bit form at least three sequential times, means for polling the means for storing a chip sequence during the three sequential times of the stored chip sequence in bit form at a clock rate of at least three times that of the clock rate of the chip sequence to ascertain whether the majority of the corresponding chips of the chip sequence stored in the means for storing from the at least three sequential times are the same to provide an output, means for comparing the output with the corresponding chip of the transmitted chip sequence to ascertain whether they are the same and with an inverted chip corresponding to the chip of the transmitted chip sequence to ascertain whether they are the same to provide compared data, means for summing the compared data to provide summed data, and adjustable threshold means for determining when the summed data constitutes a valid data bit, said means for storing consisting of a shift register having a length so that it can store at least three chip sequences, said means for polling including a plurality of circuits coupled to the shift register with a circuit being provided for each chip of the at least three chip sequences stored in the shift register, the shift register having at least three outputs for each chip of the chip sequence, and means in each of the circuits for comparing the outputs from the shift register and including an AND gate and a NOR gate and providing an output when the signals on two of the outputs on the shift register are equal, and OR gates connected to the outputs of the AND and NOR gates, first and second AND gates connected to the outputs of the OR gates, a chip of the chip sequence hard-wired into the circuit, means for supplying said chip to one of the inputs of one of the first and second AND gates, means for inverting said chip and supplying it to the other of the first and second AND gates, said first and second AND gates having X and Y outputs respectively, said means for summing the compared data including means for summing the X outputs and for summing the Y outputs independently of each other and clock means coupled to the shift register operating at a frequency which is three times the chip sequence clock rate.

3. In a correlator for use in a spread spectrum receiver for receiving encoded data which has data therein encoded with a chip sequence at a predetermined clock rate, shift register means for storing a chip sequence in coded data in bit form at least at three sequential times, a clock coupled to said shift register and having a frequency which is at least three times that of the clock rate of the chip sequence, decoding circuits coupled to the shift register and having outputs from the shift register coupled to the decoding circuits having one output for each of the three sequential times, said decoder circuit including AND and NOR gates having first and second inputs connected to two of the outputs from the shift register and providing an output signal when the inputs are equal, OR gates connected to the outputs of the AND and NOR gates, first and second AND gates connected t the outputs of the OR gates, means for supplying a chip of the chip sequence to the first and second AND gates with the chip being connected to the first AND gate in direct form and connected to the other input of the other AND gate in an inverted form, said first and second AND gates having X and Y outputs, means for summing the X outputs, means for summing the Y outputs, means for determining when the summed X outputs reach a predetermined value to decide that a valid data bit is present on the X outputs, means for ascertaining when the Y outputs reach a predetermined value to determine that a valid data bit is present on the Y outputs and means for receiving the valid data bits from the X and Y outputs for processing the same.

4. A method for use with a spread spectrum communication system for transferring data in bit form from one location to a remote location, encoding the data at one location with a chip sequence at a predetermined clock rate to provide encoded data, transmitting the encoded data to the remote location, receiving the encoded data at the remote location, storing a chip sequence in the encoded data in bit form at least at three sequential times, polling during the three sequential times the stored chip sequence in bit form at a clock rate of at least three times that of the clock rate of the chip sequence to ascertain whether a majority of the corresponding chips of the chip sequence stored during the three sequential times of stored chip sequence to ascertain whether a majority of the corresponding chips of the chip sequence stored in the three sequential times are the same to provide an output, comparing the output with the corresponding transmitted chip sequence to ascertain whether they are the same and with an inverted corresponding chip to ascertain whether they are the same to provide compared data, summing the compared data to provide summed data and ascertaining when the summed data constitutes a valid data bit.

5. A method for use with a spread spectrum communication system for transferring data in bit form by a transmitter from one location to a receiver at a remote location, supplying a chip sequence to the transmitter and the same chip sequence to the receiver, encoding the data at the transmitter with the predetermined chip sequence at a predetermined clock rate to provide encoded data, receiving the encoded data in the receiver, and examining the received encoded data at a clock rate which is at least three times that of the clock rate of the chip sequence, polling three consecutive samples to ascertain whether a majority of the corresponding samples are the same to provide improved reliability so that it can be readily ascertained when a valid data bit has been received.