System and method for phase equalization

• US 5,181,228 A
• Filed: 10/12/1990
• Issued: 01/19/1993
• Est. Priority Date: 10/12/1990
• Status: Expired due to Term

• Current Assignee: Level One Communications, Inc. (Intel Corporation)
• Original Assignee: Level One Communications, Inc. (Intel Corporation)
• Inventors: Takatori, Hiroshi
• Primary Examiner(s): Kuntz, Curtis
• Assistant Examiner(s): TSE, YOUNG TOI
• Application Number:
  US07/596,220
• Time in Patent Office: 830 Days
• Field of Search: 375/14, 375/101, 375/103, 455/206, 455/295, 455/307, 333/176, 364/724.01
• US Class Current: 375/350
• CPC Class Codes: H04B 3/146 using phase-frequency equalisers
• CPC Class Codes: H04B 3/235 combined with adaptive equaliser

Abstract

A phase equalizer in the receiver portion of a bi-directional communication system is disclosed equalizer for reducing precursor intersymbol interference without any substantial degradation in signal to noise ratio. The phase equalizer is implemented as a switched capacitor filter having a clock (switch) rate at least four times the data baud rate and a z-transfer function T(z) of a form: ##EQU1## wherein G, A, and B are fixed but adjustable coefficients.

Claims

1. A switched capacitor filter circuit for reducing precursor intersymbol interference in a digital subscriber loop, the circuit comprising:

(a) input means for accepting received data pulses;

(b) filter means, coupled to the input means, for modifying phase and amplitude characteristics of the received data pulses to create phase and amplitude modified pulses, the filter means comprising a plurality of capacitor and switch pairs coupled to an amplifier to provide a z-transfer function T(z) of a form;

##EQU6## wherein G, A and B are fixed but adjustable coefficients; and

(c) output means, coupled to the filter means, for outputting the phase and amplitude modified pulses.

2. A circuit as defined in claim 1, wherein the switched capacitor filter circuit is fabricated as a monolithic MOS integrated circuit.

3. A switched capacitor filter circuit for reducing precursor intersymbol interference comprising:

(a) input means for accepting an input 2B1Q (Two Binary One Quaternary) pulse;

(b) sampled-data means, coupled to the input means, for modifying phase and amplitude characteristics of the input 2B1Q pulse to create a modified output 2B1Q signal, and the sampled-data means comprising an operational amplifier, with at least four capacitor and switch pairs coupled thereon, for providing a z-domain transfer function of a form;

##EQU7## (c) output means, coupled to the sampled-data means, for outputting the modified output 2B1Q pulse.

4. A method for reducing precursor intersymbol interference in a digital subscriber loop having a proximal and a distal end, the method comprising the steps of:

(a) accepting pulses sent from the distal end of the loop;

(b) filtering the pulses to modify phase and magnitude characteristics thereof by applying the pulses through a switched capacitor filter having a z-transfer function T(z) of a form;

##EQU8## (c) outputting the filtered pulses in an ISDN 2B1Q format.

5. A method for reducing precursor intersymbol interference in an U-interface ISDN receiver, comprising the steps of:

(a) accepting 2B1Q (Two Binary One Quaternary) pulses;

(b) modifying magnitude and phase characteristics of the 2B1Q pulses through a switched capacitor filter according to a z-domain transfer function T(z);

##EQU9## (c) outputting the modified 2B1Q pulses.