Thin film field effect transistor array for use in active matrix liquid crystal display

• US 5,182,661 A
• Filed: 06/25/1991
• Issued: 01/26/1993
• Est. Priority Date: 06/25/1990
• Status: Expired due to Term

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Nakamura, Ken-ichi, Ikeda, Naoyasu
• Primary Examiner(s): Hille, Rolf
• Assistant Examiner(s): TRAN, MINH LOAN
• Application Number:
  US07/720,340
• Time in Patent Office: 581 Days
• Field of Search: 357/4, 357/23.7, 340/784 C, 359/54, 359/59, 359/62, 359/87, 359/88
• US Class Current: 349/38
• CPC Class Codes: G02F 1/136213 Storage capacitors associated with the pixel electrode
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors

Abstract

A thin film field effect transistor array includes several parallel gate bus lines formed on a transparent insulative substrate, and several parallel drain bus lines formed on the transparent insulative substrate so as to intersect the gate bus lines. Several pixel electrodes are each formed in proximity of a corresponding one of intersections between the gate bus lines and the drain bus lines, and several thin film field effect transistors are each formed in proximity of a corresponding one of intersections between the gate bus lines and the drain bus lines. Each of the thin film field effect transistors is connected to a corresponding one of the pixel electrodes. Several of storage capacitors are each formed in proximity of and connected in parallel to a corresponding one of the pixel electrodes. Each of the storage capacitors is formed of a stacked structure having at least first, second and third level capacitor electrodes which are stacked in the named order and separated from each other by an intervening insulating layer. At least one of the first, second and third level capacitor electrodes is connected to a corresponding one of the gate bus lines.

Claims

1. A thin film field effect transistor array comprising a transparent insulative substrate, a plurality of parallel gate bus lines formed on said transparent insulative substrate, a plurality of parallel drain bus lines formed on said transparent insulative substrate so as to intersect said gate bus lines, a plurality of pixel electrodes each formed in proximity of a corresponding one of intersections between said gate bus lines and said drain bus lines, a plurality of thin film field effect transistors each formed in proximity of a corresponding one of intersections between said gate bus lines and said drain bus lines, each of said thin film field effect transistors being connected to a corresponding one of said pixel electrodes, and a plurality of storage capacitors each formed in proximity of and connected in parallel to a corresponding one of said pixel electrodes, each of said storage capacitors being formed of a stacked structure having at least first, second and third level capacitor electrodes which are stacked in the named order and separated from each other by an intervening insulating layer, at least one of said first, second and third level capacitor electrodes being connected to a corresponding one of said gate bus lines, wherein said gate bus line is formed on the transparent insulative substrate and a first insulator layer is formed to cover said gate bus line, wherein said first level capacitor electrode is formed on said first insulator layer so as to be offset from said gate bus line and a second insulator layer is formed to cover said first level capacitor electrode, wherein said second level capacitor electrode is formed on said second insulator layer so as to partially overlap said gate bus line and said first level capacitor electrode, said second level capacitor electrode being connected to said gate bus line through a contact hole formed to pierce through said first and second insulator layers, and said third insulator layer is formed to cover said second level capacitor electrode, and wherein said third level capacitor electrode is formed of said pixel electrode which is formed on said third insulator layer so as to overlap said second level capacitor electrode, said pixel electrode being connected to said first level capacitor electrode through a contact hole formed to pierce through said second and third insulator layers.

2. The thin film field effect transistor array as claimed in claim 1, wherein said storage capacitor further includes a fourth level capacitor electrode which is an extension of said gate bus line extending underneath said first level capacitor electrode, so that said storage capacitor is of a four-layer stacked structure.

3. The thin film field effect transistor array as claimed in claim 2, wherein said fourth level capacitor electrode is formed at the same level as that of said gate bus line.

4. A thin film field effect transistor array comprising a transparent insulative substrate, a plurality of parallel gate bus lines formed on said transparent insulative substrate, a plurality of parallel drain bus lines formed on said transparent insulative substrate so as to intersect said gate bus lines, a plurality of pixel electrodes each formed in proximity of a corresponding one of intersections between said gate bus lines and said drain bus lines, a plurality of thin film field effect transistors each formed in proximity of a corresponding one of intersections between said gate bus lines and said drain bus lines, each of said thin film field effect transistors being connected to a corresponding one of said pixel electrodes, and a plurality of storage capacitors each formed in proximity of and connected in parallel to a corresponding one of said pixel electrodes, each of said storage capacitors being formed of a stacked structure having at least first, second and third level capacitor electrodes which are stacked in the named order and separated from each other by an intervening insulating layer, at least one of said first, second and third level capacitor electrodes being connected to a corresponding one of said gate bus lines, wherein said first level capacitor electrode is formed on the transparent insulative substrate underneath said gate bus line within a region between a pair of adjacent drain bus lines, and a first insulator layer is formed to cover said first level capacitor electrode, wherein said second level capacitor electrode is formed of an extension of said pixel electrode which is formed to extend over said first insulator layer above said first level capacitor electrode, and a second insulator layer is formed to cover said second level capacitor electrode, wherein said third level capacitor electrode is formed of said gate bus line formed on said second insulator layer, said gate bus line being connected to said first level capacitor electrode through a contact hole formed to pierce through said first and second insulator layers.

5. An active matrix liquid crystal display comprising:

a thin film field effect transistor array comprising a first transparent insulative substrate, a plurality of parallel gate bus lines formed on said first transparent insulative substrate, a plurality of parallel drain bus lines formed on said first transparent insulative substrate so as to intersect said gate bus lines, a plurality of pixel electrodes each formed in proximity of a corresponding one of intersections between said gate bus lines and said drain bus lines, a plurality of thin film field effect transistors each formed in proximity of a corresponding one of intersections between said gate bus lines and said drain bus lines, each of said thin film field effect transistors being connected to a corresponding one of said pixel electrodes, and a plurality of storage capacitors each formed in proximity of and connected in parallel to a corresponding one of said pixel electrodes, each of said storage capacitors being formed of a stacked structure having at least first, second and third level capacitor electrodes which are stacked in the named order and separated from each other by an intervening insulating layer, at least one of said first, second and third level capacitor electrodes being connected to a corresponding one of said gate bus lines, wherein said gate bus line is formed on the first transparent insulative substrate and a first insulator layer is formed to cover said gate bus line, wherein said first level capacitor electrode is formed on said first insulator layer so as to be offset from said gate bus line and a second insulator layer is formed to cover said first level capacitor electrode, wherein said second level capacitor electrode is formed on said second insulator layer so as to partially overlap said gate bus line and said first level capacitor electrode, said second level capacitor electrode being connected to said gate bus line through a contact hole formed to pierce through said first and second insulator layers, and said third insulator layer is formed to cover said second level capacitor electrode, and wherein said third level capacitor electrode is formed of said pixel electrode which is formed on said third insulator layer so as to overlap said second level capacitor electrode, said pixel electrode being connected to said first level capacitor electrode through a contact hole formed to pierce through said second and third insulator layers;

a second transparent insulative substrate; and

a liquid crystal disposed between said first and second transparent insulative substrates.

6. The active matrix liquid crystal display as claimed in claim 5, wherein said storage capacitor electrode includes a fourth level capacitor electrode which is an extension of said gate bus line extending underneath said first level capacitor electrode, so that said storage capacitor is of a four-layer stacked structure.

7. The active matrix liquid crystal display as claimed in claim 6, wherein said fourth level capacitor electrode is formed at the same level as that of said gate bus line.

8. The active matrix liquid crystal display as claim in claim 5, further comprising a common transparent electrode formed to cover a surface of said second transparent insulative substrate.

9. The active matrix liquid crystal display as claimed in claim 8, further comprising a color filter disposed on a surface of said common electrode.

10. The active matrix liquid crystal display as claimed in claim 9, wherein said color filter is disposed on a part of the surface of said common electrode, and wherein said liquid crystal is disposed between said color filter and said pixel electrode, and between said pixel electrode and part of said common electrode.

11. An active matrix liquid crystal display comprising:

a thin film field effect transistor array comprising a first transparent insulative substrate, a plurality of parallel gate bus lines formed on said first transparent insulative substrate, a plurality of parallel drain bus lines formed on said first transparent insulative substrate so as to intersect said gate bus lines, a plurality of pixel electrodes each formed in proximity of a corresponding one of intersections between said gate bus lines and said drain bus lines, a plurality of thin film field effect transistors each formed in proximity of a corresponding one of intersections between said gate bus lines and said drain bus lines, each of said thin film field effect transistors being connected to a corresponding one of said pixel electrodes, and a plurality of storage capacitors each formed in proximity of and connected in parallel to a corresponding one of said pixel electrodes, each of said storage capacitors being formed of a stacked structure having at least first, second and third level capacitor electrodes which are stacked in the named order and separated from each other by an intervening insulating layer, at least one of said first, second and third level capacitor electrodes being connected to a corresponding one of said gate bus lines, wherein said first level capacitor electrode is formed on the first transparent insulative substrate underneath said gate bus line within a region between a pair of adjacent drain bus lines, and a first insulator layer is formed to cover said first level capacitor electrode, wherein said second level capacitor electrode is formed of an extension of said pixel electrode which is formed to extend over said first insulator layer above said first level capacitor electrode, and a second insulator layer is formed to cover said second level capacitor electrode, wherein said third level capacitor electrode is formed of said gate bus line formed on said second insulator layer, said gate bus line being connected to said first level capacitor electrode through a contact hole formed to pierce through said first and second insulator layers;

a second transparent insulative substrate; and

a liquid crystal disposed between said first and second transparent insulative substrates.

12. The active matrix liquid crystal display as claim in claim 11, further comprising a common transparent electrode formed to cover a surface of said second transparent insulative substrate.

13. The active matrix liquid crystal display as claimed in claim 12, further comprising a color filter disposed on a surface of said common electrode.

14. The active matrix liquid crystal display as claimed in claim 13, wherein said color filter is disposed on a part of the surface of said common electrode, and wherein said liquid crystal is disposed between said color filter and said pixel electrode, and between said pixel electrode and part of said common electrode.

15. The active matrix liquid display as claimed in claim 11, wherein said display operates such that when a ratio of a storage capacitance to a liquid crystal capacitance is about 4, an aperture ratio Ap is about 61%.