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Phase measurement of received pseudonoise sequence using digital correlation

  • US 5,184,135 A
  • Filed: 03/23/1992
  • Issued: 02/02/1993
  • Est. Priority Date: 03/23/1992
  • Status: Expired due to Term
First Claim
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1. In a system where a phase modulated pseudonoise sequence signal is received, an arrangement for determining the phase of the received signal relative to the phase of a reference signal comprising:

  • means for deriving in-phase and quadrature components of the received signal relative to the reference signal;

    means utilizing said in-phase and quadrature components for quantizing the phase of the received signal in digital form as in-phase and quadrature digital signals;

    means for providing a clock signal;

    a digital correlator including;

    a) means for providing said pseudonoise sequence in digital form as an ordered sequence of M binary code elements, where M is an integer;

    b) a first shift register having M stages;

    c) a second shift register having M stages;

    d) means utilizing said clock signal for providing said in-phase digital signals as a clocked input to said first shift register;

    e) means utilizing said clock signal for providing said quadrature digital signals as a clocked input to said second shift register;

    f) a first accumulator for accumulating the sum of M inputs thereto;

    g) a second accumulator for accumulating the sum of M inputs thereto;

    h) means operating synchronously with said clock signal for providing as M inputs to said first accumulator for each stage of said first shift register the contents of that stage if the corresponding code element of the pseudonoise sequence is a binary "1" and the negative of the contents of that stage if the corresponding code element is a binary "0"; and

    i) means operating synchronously with said clock signal for providing as M inputs to said second accumulator for each stage of said second shift register the contents of that stage if the corresponding code element of the pseudonoise sequence is a binary "1" and the negative of the contents of that stage if the corresponding code element is a binary "0";

    means for obtaining the vector sum of the contents of the first and second accumulators and providing a corresponding vector sum signal; and

    peak detector means responsive to said vector sum signal for providing a time of arrival signal when the vector sum signal achieves a peak value exceeding a predetermined threshold;

    means for calculating the arctangent of the contents of the second accumulator divided by the contents of the first accumulator and providing a corresponding arctangent signal; and

    means utilizing the time of arrival signal for gating the arctangent signal as a signal representative of the phase of the received signal.

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