System with a multiport memory and N processing units for concurrently/individually executing 2N-multi-instruction-words at first/second transitions of a single clock cycle

  • US 5,203,002 A
  • Filed: 12/27/1989
  • Issued: 04/13/1993
  • Est. Priority Date: 12/27/1989
  • Status: Expired due to Fees
First Claim
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1. A digital processor for concurrently processing a plurality of instructions in a single clock cycle having at least a first transition and a second transition comprising:

  • input register means for receiving and outputting a multiinstruction word having N individually and concurrently executable instructions at said first transition of said single clock cycle, N is an integer greater than 1;

    multiport memory means, coupling to output of said input register means, for storing data and a plurality of said multiinstruction words;

    N processing means, coupling to said multiport memory means, for processing corresponding data outputted from said multiport memory means in response to said multiinstruction word outputted from said input register means, each of said N processing means concurrently and individually calculating a multiport memory write address and generating multiport memory write data for a different one of said N instructions within said multiinstruction word;

    multiplexing means, coupling to said multiport memory means and said N processing means, selectively outputting one of 2N multiinstruction words received from said multiport memory means based upon signals received from said N processing means wherein said multiport memory means outputting said 2N of said multiinstruction words to said multiplexing means in response to the output from said input register means and output from said N processing means; and

    ,output register means, coupling to input of said input register means and output of said multiplexing means, for holding said outputted multiinstruction word at said second transition of said single clock cycle.

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