Synaptic element including weight-storage and weight-adjustment circuit

• US 5,204,549 A
• Filed: 01/28/1992
• Issued: 04/20/1993
• Est. Priority Date: 01/28/1992
• Status: Expired due to Term

• Current Assignee: Synaptics Incorporated
• Original Assignee: Synaptics Incorporated
• Inventors: Platt, John C., Mead, Carver A., Anderson, Janeen D. W.
• Primary Examiner(s): Hudspeth, David R.
• Assistant Examiner(s): SANTAMAURO, JON P
• Application Number:
  US07/827,005
• Time in Patent Office: 448 Days
• Field of Search: 307/201, 307/529, 307/570, 307/450, 395/24
• US Class Current: 706/33
• CPC Class Codes: G06N 3/065 Analogue means

Abstract

A weight-storage and weight-adjustment circuit includes a first hot electron injection device coupled to a first floating gate and a second hot electron injection device coupled to the second floating gate. The floating gates are associated with two series connected MOS transistors. The first and second hot electron injection devices comprise gated lateral bipolar transistors. The weight may be decreased by injecting hot electrons from the first hot electron injection device onto the first floating gate to decrease the first analog voltage and increased by injecting electrons from the second hot electron injection device onto the second floating gate to decrease the second analog voltage. Circuitry are provided to periodically adjust the absolute voltage levels on the first and second floating gates to prevent them from becoming too negative over time. First and second electron tunneling devices are coupled to the first and second floating gates, respectively, to simultaneously adjust the voltages stored on the floating gates to keep them within a desired voltage range.

Claims

1. A synaptic element including a weight-storage and weight-adjustment circuit, comprising:

an input node;

a positive output node;

a negative output node;

a first floating node;

a second floating node;

a first MOS transistor, having a source connected to said positive output node, a drain connected to said input node, and a gate comprising at least a portion of said first floating node;

a second MOS transistor having a source connected to said input node, a drain connected to said negative output node, and a gate comprising at least a portion of said second floating node;

first means for injecting electrons onto said first floating node;

second means for injecting electrons onto to said second floating node;

third means for simultaneously removing essentially the same number of electrons from said first and second floating nodes to maintain them within a desired voltage range;

means for comparing an output signal at said output node with a desired output signal and for generating a positive error signal if said output signal is more positive than said desired output signal and for generating a negative error signal if said output signal is more negative than said desired output signal;

means for generating a positive-input-present-signal if a positive input signal is present at said input node and for generating a negative-input-signal-present if a negative signal is present at said input node;

means for defining a weight-update interval;

means responsive to the simultaneous presence of said positive error signal and said positive-input-present-signal and active during said weight-update interval, for activating said first means for injecting electrons onto said first floating node at a rate proportional to the product of said positive error signal and said positive-input-present-signal;

means responsive to the simultaneous presence of said positive error signal and said negative-input-present-signal and active during said weight-update interval, for activating said second means for injecting electrons onto said second floating node at a rate proportional to the product of said positive error signal and said negative-input-present-signal;

means responsive to the simultaneous presence of said negative error signal and said positive-input-present-signal and active during said weight-update interval, for activating said second means for injecting electrons onto said second floating node at a rate proportional to the product of said negative error signal and said positive-input-present-signal;

means responsive to the simultaneous presence of said negative error signal and said negative-input-present-signal and active during said weight-update interval, for activating said first means for injecting electrons onto said first floating node at a rate proportional to the product of said negative error signal and said negative-input-present-signal.

2. The synaptic element of claim 1 wherein said first and second means are non-avalanche hot electron injection devices and wherein said third means comprises tunneling devices.

3. In a synaptic array, a synaptic element including a weight-storage and weight-adjustment circuit, comprising:

an input node;

a positive output node;

a negative output node;

a first floating node, at least a portion of which comprises the gate of at least a first MOS transistor of said synaptic element;

a second floating node, at least a portion of which comprises the gate of at least a second MOS transistor of said synaptic element;

first means for injecting electrons onto said first floating node;

second means for injecting electrons onto to said second floating node;

third means for simultaneously removing essentially the same number of electrons from said first and second floating nodes to maintain them within a desired voltage range;

means for comparing an output signal at a selected node in said array with a desired output signal and for generating a positive error signal if said output signal is more positive than said desired output signal and for generating a negative error signal if said output signal is more negative than said desired output signal;

means for generating a positive-input-present-signal if a positive input signal is present at said input node and for generating a negative-input-signal-present if a negative signal is present at said input node;

means for defining a weight-update interval;

means responsive to the simultaneous presence of said positive error signal and said positive-input-present-signal and active during said weight-update interval, for activating said first means for injecting electrons onto said first floating node at a rate proportional to the product of said positive error signal and said positive-input-present-signal;

means responsive to the simultaneous presence of said positive error signal and said negative-input-present-signal and active during said weight-update interval, for activating said second means for injecting electrons onto said second floating node at a rate proportional to the product of said positive error signal and said negative-input-present-signal;

means responsive to the simultaneous presence of said negative error signal and said positive-input-present-signal and active during said weight-update interval, for activating said second means for injecting electrons onto said second floating node at a rate proportional to the product of said negative error signal and said positive-input-present-signal;

means responsive to the simultaneous presence of said negative error signal and said negative input-present-signal and active during said weight-update interval, for activating said first means for injecting electrons onto said first floating node at a rate proportional to the product of said negative error signal and said negative-input-present-signal.

4. The synaptic element of claim 3 wherein said first and second means are non-avalanche hot electron injection devices and wherein said third means comprises tunneling devices.

5. A synaptic array including:

a plurality of synaptic elements arranged in at least one row and at least one column, each of said first synaptic elements including an input node, a positive output node, a negative output node, a first floating node, a second floating node, a first MOS transistor having a source connected to said positive output node, a drain connected to said input node, and a gate comprising at least a portion of said second first floating node, a second MOS transistor having a source connected to said input node, a drain connected to said negative output node, and a gate comprising at least a portion of said second floating node, a first hot-electron injector for injecting electrons onto said first floating node, said first hot-electron injector comprising a gated bipolar transistor having a gate electrically connected to said floating node, an emitter connected to a fixed voltage source, a base, and a collector, a second hot-electron injector for injecting electrons onto said second floating node, said second hot-electron injector comprising a gated bipolar transistor having an emitter connected to a fixed voltage source, a gate electrically connected to said floating node, a base, and a collector, and means for simultaneously removing essentially the same number of electrons from said first and second floating nodes to maintain them within a desired voltage range;

a plurality of signal input lines, a unique one of said signal input lines associated with each of said rows, each unique one of said signal input lines connected to the input nodes of each of said synaptic elements associated with its row;

a plurality of positive output lines, a unique one of said positive output lines associated with each of said columns, each unique one of said positive output lines connected to the positive output nodes of each of said synaptic elements associated with its column;

a plurality of negative output lines, a unique one of said negative output lines associated with each of said columns, each unique one of said negative output lines connected to the negative output nodes of each of said synaptic elements associated with its column;

a plurality of positive current sense amplifiers, a unique one of said positive current sense amplifiers driven by one of said positive output lines;

a plurality of negative current sense amplifiers, a unique one of said negative current sense amplifiers driven by one of said negative output lines;

a plurality of first error lines, a unique one of said first error lines associated with each of said columns, each unique one of said first error lines connected to the collector of the first hot-electron injector of each of said synaptic elements associated with its column;

a plurality of second error lines, a unique one of said second error lines associated with each of said columns, each unique one of said second error lines connected to the collector of the second hot-electron injector of each of said synaptic elements associated with its column;

a plurality of update input lines, a unique one of said update input lines associated with each of said rows, each unique one of said update input lines connected to the bases of said first and second hot-electron injectors of each of said synaptic elements associated with its row;

means for individually summing the outputs of said positive and negative current sense amplifiers associated with each of said columns to produce a column output signal;

means for comparing each column output signal with a desired output signal and for generating a positive error signal if said column output signal is more positive than said desired output signal and for generating a negative error signal if said column output signal is more negative than said desired output signal;

means, associated with each of said signal input lines, for generating a positive-input-present-signal if a positive input signal is present on said signal input line and for generating a negative-input-signal-present signal if a negative input signal is present on said signal input line;

means for defining a weight-update interval;

means, associated with each of said columns, responsive to the simultaneous presence of said positive error signal and said positive-input-present-signal and active during said weight-update interval, for activating said first means for injecting electrons onto said first floating nodes associated with each column at a rate proportional to the product of said positive error signal and said positive-input-present-signal associated with each column;

means, associated with each of said columns, responsive to the simultaneous presence of said positive error signal and said negative-input-present-signal and active during said weight-update interval, for activating said second means for injecting electrons onto said second floating nodes associated with each column at a rate proportional to the product of said positive error signal and said negative-input-present-signal associated with each column;

means responsive to the simultaneous presence of said negative error signal and said positive-input-present-signal and active during said weight-update interval, for activating said second means for injecting electrons onto said second floating nodes associated with each column at a rate proportional to the product of said negative error signal and said positive-input-present-signal associated with each column;

means responsive to the simultaneous presence of said negative error signal and said negative-input-present-signal and active during said weight-update interval, for activating said first means for injecting electrons onto said first floating nodes associated with each column at a rate proportional to the product of said negative error signal and said negative-input-present-signal associated with each column.

6. The synaptic array of claim 5 wherein said third means comprises tunneling devices.