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System for updating program stored in EEPROM by storing new version into new location and updating second transfer vector to contain starting address of new version

  • US 5,210,854 A
  • Filed: 06/14/1989
  • Issued: 05/11/1993
  • Est. Priority Date: 06/14/1989
  • Status: Expired due to Term
First Claim
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1. A digital computer memory system comprising:

  • an electrically erasable programmable read-only memory containing firmware, having a plurality of address and data inputs and a plurality of locations, each location having an address, and a control input which permits writing to the electrically erasable programmable read-only memory, the electrically erasable programmable read-only memory is partitioned into a protected area and an unprotected area, the unprotected area having a conditionally writable area;

    a central processing unit having a plurality of data outputs, a plurality of address outputs, a control output and an update enable output;

    an address bus coupling the plurality of address inputs in the electrically erasable programmable read-only memory to the plurality of address outputs of the central processing unit;

    a data bus coupling the plurality of data inputs in the electrically erasable programmable read-only memory to the plurality of data outputs of the central processing unit; and

    a control logic device having a plurality of address inputs, a control input, an update enable input and an output, the plurality of address inputs coupled to at least a portion of the address bus, the output coupled to the control input of the electrically erasable programmable read-only memory, the control input coupled to the control output of the central processing unit, and the update enable input coupled to the update enable output of the central processing unit;

    the control logic device responsive to the control output of the central processing unit and an address transmitted on the at least a portion of the address bus, generating a write enable signal when the address is within the unprotected area of the electrically erasable programmable read-only memory and inhibiting the write enable signal when the address is within the protected area of the electrically erasable programmable read-only memory;

    the control logic device generating in response to the control input, the update enable input and the address transmitted on the at least a portion of the address bus, a write enable signal when the address is within the conditionally writable area of the electrically erasable programmable read-only memory and inhibiting the write enable signal when the address is within the protected area of the electrically erasable programmable read-only memory.

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