Wormhole communications arrangement for massively parallel processor

  • US 5,212,773 A
  • Filed: 02/22/1991
  • Issued: 05/18/1993
  • Est. Priority Date: 05/31/1983
  • Status: Expired due to Term
First Claim
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1. A computer system comprising a plurality of processing elements and a message router in which:

  • A. each processing element for generating messages, each message comprising an address portion comprising a series of address elements and a data portion comprising at least one data element, each processing element including a message transfer circuit for transmitting messages over said message router and for receiving messages from said router, said message transfer circuit transmitting each message by serially transmitting address elements and a data element thereof and receiving a message by serially receiving at least a data element thereof;

    B. said message router being connected to the message transfer circuits of said processing elements for receiving messages transmitted by said message transfer circuits and transferring each such received message to a processing element in accordance with its address portion, said message router comprising a plurality of message router nodes interconnected by a plurality of communications links, at least some of said message router nodes also being connected to said processing elements, said message router nodes each including;

    i. a plurality of input circuits each connected to one of said communications links or said processing elements for receiving messages therefrom, each input circuit serially receiving message elements comprising each message received thereby;

    ii. a plurality of output circuits each connected to a communications link or to a processing element for transmitting messages thereto, each output circuit serially transmitting message elements comprising each message transmitted thereto; and

    iii. a switch connected to said input circuits for, for each message received by said input circuits, decoding one address element of the message to identify therefor an output circuit, said switch establishing a path for said message between the input circuit which received the message and the identified output circuit to facilitate the transfer of message elements of said message therebetween, said switch maintaining the path until the last of the serially-received message elements for the message have been transferred to the identified output circuit.

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