Semiconductor power devices with alternating conductivity type high-voltage breakdown regions

• US 5,216,275 A
• Filed: 09/17/1991
• Issued: 06/01/1993
• Est. Priority Date: 03/19/1991
• Status: Expired due to Term

• Current Assignee: Third Dimension Semiconductor Incorporated
• Original Assignee: University of Electronic Science and Technology of China
• Inventors: Chen, Xingbi
• Primary Examiner(s): Jackson, Jr., Jerome
• Application Number:
  US07/761,407
• Time in Patent Office: 623 Days
• Field of Search: 357/20, 357/23.8
• US Class Current: 257/493
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/73 Bipolar junction transistors
• CPC Class Codes: H01L 29/7392 with PN junction gate, e.g. field controlled thyristors (FCTh), static induction thyristors (SITh)
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/861 Diodes

Abstract

A semiconductor power device wherein the reverse voltage across the p⁺ -regions(s) and the n⁺ -regions(s) is sustained by a composite buffer layer, shortly as CB-layer. The CB-layer contains two kinds of semiconductor regions with opposite types of conduction. These two kinds of regions are alternatively arranged, viewed from any cross-section parallel to the interface between the layer itself and the n⁺ (or p⁺)-region. Whereas the hitherto-used voltage sustaining layer contains only one kind of semiconductor with single type of conduction in the same sectional view. Design guidelines are also provided in this invention. The relation between the on-resistance in unit area Ron and the breakdown voltage V_B of the CB-layer invented is Ron ocV_B¹¹³ which represents a breakthrough to the conventional voltage sustaining layer, whereas the other performances of the power devices remain almost unchanged.

Claims

1. A semiconductor power device comprising:

a first contact layer of a first conductivity type;

a second contact layer of a second conductivity type; and

a voltage sustaining layer between said first and second contact layers, said voltage sustaining layer comprising first semiconductor regions of the first conductivity type and second semiconductor regions of a second conductivity type, said first and second semiconductor regions being alternately arranged, the voltage sustaining layer further comprising a thin dielectric layer located between one of said first semiconductor regions and one of said second semiconductor regions for isolating said one of said first semiconductor regions and said one of said second semiconductor regions, the first contact layer contacting said first semiconductor region forming a first interface, the second contact layer contacting the first and second semiconductor regions directly forming a second interface.

2. The semiconductor power device according to claim 1, wherein the first contact layer is isolated from the second semiconductor regions by a second thin dielectric layer.

3. The semiconductor device of claim 1, wherein said first and second interfaces are parallel to each other and perpendicular to the plane of the dielectric layer between said one of said first semiconductor regions and said one of said second semiconductor regions, and wherein the first and second semiconductor regions are shaped in a manner that in a cross-section of the voltage sustaining layer parallel to the first and second interface, the first and second semiconductor regions are square-shaped and form a mosaic pattern.

4. The semiconductor device of claim 1, wherein said first and second interfaces are parallel to each other and perpendicular to the plane of the dielectric layer between said one of said first semiconductor regions and said one of said second semiconductor regions, and wherein the first and second semiconductor regions are shaped in a manner that in a cross-section of the voltage sustaining layer parallel to the first and second interface, one of the first semiconductor regions and one of the second semiconductor regions form a close-packed hexagonal unit, and the dielectric layer forms a circle about the center of the hexagonal unit with one of said first (or second) semiconductor regions within the circle and one of said second (or first) semiconductor regions outside the circle.

5. The semiconductor device of claim 1, wherein the first contact layer is an n⁺ layer, the second contact layer is a p⁺ layer, the first semiconductor regions are n regions and the second semiconductor regions are p regions.

6. The semiconductor device of claim 1, wherein the first contact layer is a p⁺ layer, the second contact layer is an n⁺ layer, the first semiconductor regions are p regions and the second semiconductor regions are n regions.

7. The semiconductor power device according to claim 1, wherein the first and second semiconductor regions are doped with dopants and the total charge of the effective dopant concentration in the first semiconductor region does not exceed the total charge of the effective dopant concentration of the second semiconductor region by 50%.

8. The semiconductor power device according to claim 6, wherein the cross-sectional area of each first semiconductor region is not equal to each second semiconductor region.

9. The semiconductor power device according to claim 1, wherein the first and second semiconductor regions are doped with dopants and the effective charge distribution of dopants in every region of the voltage sustaining layer is uniform.

10. The semiconductor power device according to claim 1, wherein the first and second semiconductor regions are doped with dopants and the effective dopant distribution in every region in the voltage sustaining region is non-uniform, the dopant concentration in the first semiconductor regions is greater near the first contact layer than near the second contact layer, and the dopant concentration in the second semiconductor regions is greater near the second contact layer than near the first contact layer.

11. A semiconductor power device comprising:

a first contact layer of a first conductivity type;

a second contact layer of a second conductivity type; and

a voltage sustaining layer between said first and second contact layers, said voltage sustaining layer comprising first semiconductor regions of the first conductivity type and second semiconductor regions of a second conductivity type, said first and second semiconductor regions being alternately arranged, the first contact layer contacting all said first semiconductor regions and said second semiconductor regions to form a first interface, the second contact layer contacting with all the first and second semiconductor regions to form a second interface wherein the first and second semiconductor regions are doped with dopants and the effective dopant distribution in every region in the voltage sustaining region is non-uniform, the dopant concentration in the first semiconductor regions is greater near the first contact layer than near the second contact layer and the dopant concentration in the second semiconductor regions is greater near the second contact layer than near the first contact layer.

12. The semiconductor device of claim 11, wherein the first contact layer is an n⁺ layer, the second contact layer is a p⁺ layer, the first semiconductor regions are n regions doped with donors and the second semiconductor regions are p regions doped with acceptors.

13. The semiconductor device of claim 11, wherein the doped first contact layer is a p⁺ layer, the second contact layer is an n⁺ layer, the first semiconductor regions are p regions doped with acceptors and the second semiconductor regions are n regions doped with donors.

14. A semiconductor power device comprising:

a first contact layer of a first conductivity type;

a second contact layer of a second conductivity type; and

a voltage sustaining layer between said first and second contact layers, said voltage sustaining layer comprising first semiconductor regions of the first conductivity type and second semiconductor regions of a second conductivity type which are alternately arranged, the first contact layer contacting all said first semiconductor regions and said second semiconductor regions to form a first interface, the second contact layer contacting with all the first and second semiconductor regions directly to form a second interface wherein said first and second interface are parallel to each other and wherein the first and second semiconductor regions are shaped in a manner that in a cross-section of the voltage sustaining layer parallel to the first and second interface, one of the first semiconductor regions and one of the second semiconductor regions form a close packed hexagonal unit, the first semiconductor region is within a circle about the center of the close-packed hexagonal unit and one of said second semiconductor regions is outside the circle.

15. The semiconductor device of claim 14, wherein the first contact layer is an n⁺ layer, the second contact layer is a p⁺ layer, the first semiconductor regions are n regions and the second semiconductor regions are p regions.

16. The semiconductor device of claim 14, wherein the first contact layer is a p⁺ layer, the second contact layer is an n⁺ layer, the first semiconductor regions are p regions and the second semiconductor regions are n regions.

17. A semiconductor power device comprising:

a first contact layer of a first conductivity type;

a second contact layer of a second conductivity type; and

a voltage sustaining layer between said first and second contact layers, said voltage sustaining layer comprising first semiconductor regions of the first conductivity type and second semiconductor regions of a second conductivity type, said first and second semiconductor regions being alternately arranged, the first contact layer contacting said first semiconductor regions and said second semiconductor regions to form a first interface, the second contact layer contacting with all the first and second semiconductor regions directly to form a second interface wherein said first and second interface are parallel to each other and wherein the first and second semiconductor regions are shaped in a manner that in a cross-section of the voltage sustaining layer parallel to the first and second interface, the first and second semiconductor regions are square-shaped and form a mosaic pattern.

18. The semiconductor device of claim 17, wherein the first contact layer is an n⁺ layer, the second contact layer is a p⁺ layer, the first semiconductor regions are n regions and the second semiconductor regions are p regions.

19. The semiconductor device of claim 17, wherein the first contact layer is a p⁺ layer, the second contact layer is an n⁺ layer, the first semiconductor regions are p regions and the second semiconductor regions are n regions.