Cascaded switching and series regulators

• US 5,216,351 A
• Filed: 05/10/1991
• Issued: 06/01/1993
• Est. Priority Date: 05/16/1990
• Status: Expired due to Term

• Current Assignee: Seiko Instruments Incorporated (Seiko Group)
• Original Assignee: Seiko Instruments Incorporated (Seiko Group)
• Inventors: Shimoda, Sadashi
• Primary Examiner(s): BEHA JR, WILLIAM
• Application Number:
  US07/698,593
• Time in Patent Office: 753 Days
• Field of Search: 323/222, 323/224, 323/266, 323/268, 323/273, 323/274, 323/282, 323/284, 363/124
• US Class Current: 323/224
• CPC Class Codes: G05F 1/563 including two stages of regulation at least one of which is output level responsive, e.g. coarse and fine regulation
• CPC Class Codes: G05F 1/62 using bucking or boosting dc sources
• CPC Class Codes: H02M 1/0045 Converters combining the concepts of switch-mode regulation and linear regulation, e.g. linear pre-regulator to switching converter, linear and switching converter in parallel, same converter or same transistor operating either in linear or switching mode
• CPC Class Codes: H02M 3/156 with automatic control of output voltage or current, e.g. switching regulators

Abstract

The voltage regulator of the boosting/lowering type is comprised of a switching regulator block and a series regulator block, which are cascade-connected to each other. One input terminal of an error amplifier of the switching regulator block is connected to a dividing node of bleeder resistors in the series regulator block to constitute a regulative feedback loop effective to improve an efficiency of the voltage regulator.

Claims

1. A voltage regulator comprising:

a leading switching regulator block including a first error amplifier having input terminals, an oscillating circuit, a switching transistor receiving a signal from the oscillating circuit in accordance with a signal from the first error amplifier and a coil connected to the switching transistor; and

a following series regulator block including a control transistor, and bleeder resistors for feeding back a regulative voltage to one of the input terminals of the first error amplifier and to the gate of the control transistor for effecting a voltage drop from the output from the leading switching regulator block controlled by the regulative voltage.

2. A voltage regulator as claimed in claim 1, wherein the gate of the control transistor is connected to an output terminal of a second error amplifier included in the following series regulator block.

3. A voltage regulator as claimed in claim 2, wherein one of the input terminals of the second error amplifier is connected to a junction node between the bleeder resistors.

4. A voltage regulator comprising:

first regulating means receptive of an input voltage for producing a boosted intermediate level voltage output; and

second regulating means receptive of the intermediate level voltage output for producing a lower regulated voltage output, the second regulating means comprising a control transistor receptive of the intermediate level voltage for effecting a voltage drop thereacross to produce the regulated voltage output and having a gate input for determining the voltage drop, and control means receptive of the regulated voltage output for producing a control signal corresponding to the regulated voltage and for applying the control signal to the gate of the control transistor.

5. A voltage regulator according to claim 4, wherein the means for producing the control signal comprises bleeder resistors receptive of the regulated voltage output to divide same, and means for applying the divided voltage to the gate of the control transistor.

6. A voltage regulator according to claim 5, wherein the first regulating means comprises an error amplifier receptive of the divided voltage and a reference voltage, a switching transistor receptive of an output from an oscillating circuit and the error amplifier, and a coil connected to the switching transistor for boosting the input voltage.

7. A voltage regulator according to claim 5, wherein the means for applying the divided voltage comprises a second error amplifier receptive of the divided voltage and a reference voltage.