Methodology for deriving executable low-level structural descriptions and valid physical implementations of circuits and systems from high-level semantic specifications and descriptions thereof

  • US 5,222,030 A
  • Filed: 04/06/1990
  • Issued: 06/22/1993
  • Est. Priority Date: 04/06/1990
  • Status: Expired due to Term
First Claim
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1. In an ECAD system, a method of creating and validating a structural description of a circuit or device from a higher level, behavior-oriented description thereof, comprising:

  • entering on an ECAD system a specification for a design of desired behavior of a device, including high-level timing goals, in a high level, behavior-oriented language;

    on the ECAD system, iteratively simulating and changing the design of the device at the behavioral-level until the desired behavior is obtained;

    on the ECAD system, partitioning the design of the device into a number of architectural blocks and constraining the architectural choices to those which meet the high-level timing goals, andon the ECAD system, directing the various architectural blocks to logic synthesis programs, said logic synthesis programs also running in the ECAD system, thereby providing a netlist or gate-level description of the design.

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