Semiconductor memory circuit device and method for fabricating same

• US 5,237,187 A
• Filed: 11/27/1991
• Issued: 08/17/1993
• Est. Priority Date: 11/30/1990
• Status: Expired due to Term

• Current Assignee: Semiconductor Patent Corporation
• Original Assignee: Hitachi, Ltd.
• Inventors: Watanabe, Kozo, Uchiyama, Hiroyuki, Kaneko, Yoshiyuki, Yoneoka, Takashi, Suwanai, Naokatsu, Endo, Kazuya, Miyazawa, Hiroyuki, Asayama, Kyoichiro, Ogishima, Atushi, Nagao, Masaki, Soeda, Hiroki
• Primary Examiner(s): LaRoche, Eugene R.
• Assistant Examiner(s): Nguyen, Viet Q.
• Application Number:
  US07/799,541
• Time in Patent Office: 629 Days
• Field of Search: 357/23.4, 357/23.6, 357/54, 257/68, 257/71, 257/288, 257/298, 257/300, 257/314
• US Class Current: 257/296
• CPC Class Codes: H10B 12/01 Manufacture or treatment
• CPC Class Codes: H10B 12/30 DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
• CPC Class Codes: H10B 12/31 having a storage electrode stacked over the transistor

Abstract

In a semiconductor memory circuit device wherein each memory cell is constituted by a series circuit of a memory cell selecting MISFET and an information storing capacitor of a stacked structure, there are present in a first region, which is a memory cell array region, a first MISFET having a gate electrode and source and drain regions; first and second capacitor electrodes and a dielectric film extended over a first insulating film and over the gate electrode; a second insulating film disposed on the second capacitor electrode; a third insulating film interposed between the first insulating film and first capacitor electrode; and a first wiring positioned on the second insulating film. In a second region of the device, which is a peripheral circuit region, there are present a second MISFET having a gate electrode and source and drain regions; a first insulating film on the gate electrode; a second insulating film on a third insulating film, the third insulating film being interposed between the first and second insulating films; and a second wiring on the second insulating film. The second wiring is formed by the same level conductor layer as that forming the first wiring. Similarly, the first through third insulating films of the first region are correspondingly associated with the first through third insulating films of the second region, respectively.

Claims

1. A semiconductor memory circuit device comprising:

a semiconductor substrate having a main surface and an opposing, back surface, wherein at said main surface there are provided a first region including a memory cell array, and a separate, second region including peripheral circuitry;

a first MISFET formed in said first region and comprising a gate electrode and source and drain regions;

a second MISFET formed in said second region and comprising a gate electrode and source and drain regions;

a first insulating film disposed on the gate electrode of each of said first and second MISFETs;

a first capacitor electrode connected electrically to one of the source and drain regions of said first MISFET and extending onto said first insulating film and over the gate electrode of said first MISFET;

a second capacitor electrode disposed on a dielectric film formed on said first capacitor electrode;

a second insulating film disposed on said second capacitor electrode in said first region and over said first insulating film in said second region;

a conductor layer including a first wiring disposed on said second insulating film and over the gate electrode of said first MISFET, in said first region, and a second wiring disposed on said second insulating film and over the gate electrode of said second MISFET, in said second region; and

a third insulating film interposed between said first insulating film and said first capacitor electrode in said first region, and between said first and second insulating films in said second region.

2. A semiconductor memory circuit device according to claim 1, wherein said third insulating film is a silicon dioxide film.

3. A semiconductor memory circuit device according to claim 1, wherein said third insulating film, in said first region, is extended to be on said first insulating film and over the gate electrode of said first MISFET.

4. A semiconductor memory circuit device according to claim 1, wherein said first and second capacitor electrodes are extended to overlie said first insulating film in said first region.

5. A semiconductor memory circuit device according to claim 1, wherein said conductor layer for providing said first and second wirings includes a high melting metal.

6. A semiconductor memory circuit device according to claim 1, wherein said conductor layer for providing said first and second wirings includes a silicide of a high melting metal.

7. A semiconductor memory circuit device according to claim 1, wherein said first wiring provides a data line.

8. A semiconductor memory circuit device according to claim 7, wherein said first wiring is connected to the other of the source and drain regions of said first MISFET.

9. A semiconductor memory circuit device according to claim 1, wherein the difference in the height distances as measured from the back surface of said semiconductor substrate to said first and second wirings, respectively, is not larger than 1.5 μ

m.

10. A semiconductor memory circuit device comprising:

a semiconductor substrate having a main surface and an opposing, back surface, wherein at said main surface there are provided first and second regions;

a memory cell array formed in said first region and including a plurality of memory cells arranged in a matrix form;

peripheral circuitry formed in said second region and comprising a plurality of MISFETs each having a gate electrode and source and drain regions; and

a conductor layer including first wirings and second wirings,

wherein said first wirings are disposed in said first region and said second wirings are disposed in said second region, said first and second wirings are used for connections to the source or drain region of each said MISFET in said first and second regions, respectively, and

wherein the difference in the height distances as measured from the back surface of said semiconductor substrate to said first and second wirings, respectively, is not larger than 1.5 μ

m.