Linear and orthogonal expansion of array storage in multiprocessor computing systems
First Claim
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1. A multiprocessing computer system comprising:
 a. a plurality of processing units;
b. at least one data storage array system, each having at least one array controller;
c. switching network means, coupled to the plurality of processing units and to at least one array controller of at least one data storage array system, for establishing a communications link between at least one selected processing unit and at least one data storage array system.
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Abstract
A multiprocessing computer system with data storage array systems allowing for linear and orthogonal expansion of data storage capacity and bandwidth by means of a switching network coupled between the data storage array systems and the multiple processors. The switching network provides the ability for any CPU to be directly coupled to any data storage array. By using the switching network to couple multiple CPU'"'"'s to multiple data storage array systems, the computer system can be configured to optimally match the I/O bandwidth of the data storage array systems to the I/O performance of the CPU'"'"'s.
186 Citations
34 Claims

1. A multiprocessing computer system comprising:

a. a plurality of processing units; b. at least one data storage array system, each having at least one array controller; c. switching network means, coupled to the plurality of processing units and to at least one array controller of at least one data storage array system, for establishing a communications link between at least one selected processing unit and at least one data storage array system.  View Dependent Claims (2, 3, 8, 9, 10)


4. A linearly and orthogonally expandable multiprocessing computer system comprising:

a. at least two processing units, each processing unit having a respective input/output data transfer rate; b. at least one interprocessor bus for intercoupling the at least two processing units, the at least one bus having sufficient capacity to be coupled to at least one additional processing unit; c. at least one data storage array system including at least two data storage units, at least one data storage array system having sufficient capacity to be coupled to at least one additional processing unit, each data storage array system having a respective input/output data transfer rate; d. switching network means, coupled to the processing units and to at least one data storage array system, for establishing a communications link between at least one selected processing unit and at least one data storage array system, the switching network means having an input/output data transfer rate; wherein the input/output data transfer rate of the switching network means at least equals the sum of input/output data transfer rates of either the processing units or the data storage array systems, and additional data storage units may be added to at least one data storage array system to increase the sum of the input/output data transfer rates of the data storage array systems, and additional processing units may be added to the interprocessor bus to increase the sum of the input/output data transfer rates of the processing units.  View Dependent Claims (5, 6, 7)


11. A multiprocessing computer system comprising:

a. a plurality of processing units; b. at least one data storage array system, each having at least one array controller; c. at least two switching network means, each coupled to the plurality of processing units and to at least one array controller of at least one data storage array system, for establishing a redundant communications link between at least one selected processing unit and at least one data storage array system.  View Dependent Claims (12, 13)


14. A multiprocessing computer system comprising:

a. a plurality of processing units; b. at least one data storage array system, each having at least one array controller; c. at least one switching network, coupled to the plurality of processing units and to at least one array controller of at least one data storage array system, for establishing a communications link between at least one selected processing unit and at least one data storage array system.  View Dependent Claims (15, 16, 17, 18, 19)


20. A linearly and orthogonally expandable multiprocessing computer system comprising:

a. at least two processing units, each processing unit having a respective input/output data transfer rate; b. at least one interprocessor bus for intercoupling the at least two processing units, the at least one bus having sufficient capacity to be coupled to at least one additional processing unit; c. at least one data storage array system including at least two data storage units, at least one data storage array system having sufficient capacity to be coupled to at least one additional processing unit, each data storage array system having a respective input/output data transfer rate; d. at least one switching network, coupled to the processing units and to at least one data storage array system, for establishing a communications link between at least one selected processing unit and at least one data storage array system, each switching network having an input/output data transfer rate; wherein the input/output data transfer rate of at least one switching network at least equals the sum of input/output data transfer rates of either the processing units or the data storage array systems, and additional data storage units may be added to at least one data storage array system to increase the sum of the input/output data transfer rates of the data storage array systems, and additional processing units may be added to the interprocessor bus to increase the sum of the input/output data transfer rates of the processing units.  View Dependent Claims (21, 22, 23)


24. A multiprocessing computer system comprising:

a. a plurality of processing units; b. at least one data storage array system, each having at least one array controller; c. at least two switching networks, each coupled to the plurality of processing units and to at least one array controller of at least one data storage array system, for establishing a redundant communications link between at least one selected processing unit and at least one data storage array system.  View Dependent Claims (25, 26)


27. A data storage system for connection to a multiprocessing computer system including a plurality of processing units, the data storage system comprising:

a. at least one data storage array system, each having at least one array controller; b. at least one switching network, adapted to be coupled to the plurality of processing units and to at least one array controller of at least one data storage array system, for establishing a communications link between at least one selected processing unit and at least one data storage array system.  View Dependent Claims (28, 29, 30)


31. A linearly and orthogonally expandable data storage system for connection to a multiprocessing computer system comprising at least two processing units, each processing unit having a respective input/output data transfer rate, and at least one interprocessor bus for intercoupling the at least two processing units, the at least one bus having sufficient capacity to be coupled to at least one additional processing unit, the data storage system comprising:

a. at least one data storage array system including at least two data storage units, at least one data storage array system having sufficient capacity to be coupled to at least one additional processing unit, each data storage array system having a respective input/output data transfer rate; b. at least one switching network, adapted to be coupled to the processing units and to at least one data storage array system, for establishing a communications link between at least one selected processing unit and at least one data storage array system, the switching network having an input/output data transfer rate; wherein the input/output data transfer rate of at least one switching network at least equals the sum of input/output data transfer rates of either the processing units or the data storage array systems, and additional data storage units may be added to at least one data storage array system to increase the sum of the input/output data transfer rates of the data storage array systems, and additional processing units may be added to the interprocessor bus to increase the sum of the input/output data transfer rates of the processing units.  View Dependent Claims (32, 33, 34)

1 Specification