Integrated device for recognition of moving objects

• US 5,248,873 A
• Filed: 09/01/1992
• Issued: 09/28/1993
• Est. Priority Date: 06/10/1991
• Status: Expired due to Term

• Current Assignee: Synaptics Incorporated
• Original Assignee: Synaptics Incorporated
• Inventors: Allen, Timothy P., Faggin, Federico
• Primary Examiner(s): Nelms, David C.
• Application Number:
  US07/939,108
• Time in Patent Office: 392 Days
• Field of Search: 250/206.1, 250/206.2, 250/208.1, 250/561, 250/566, 382/68, 382/33, 382/36, 382/39
• US Class Current: 250/208.1
• CPC Class Codes: G06V 10/10 Image acquisition document image scanning and transmission H04N1/00; control of digital cameras H04N23/60

Abstract

A moving object classifier is integrated onto a single integrated circuit chip and includes a retina comprising a two-dimensional array of photosensors upon which the image of the object of interest is focused. A position classifier receives inputs from the retina and determines where in the retina the image of an object is located. An object classifier receives inputs from the portion of interest of the retina and computes the degree of membership of the image to each class to be classified and determines which class has the largest membership function. A scan controller controlled by the position classifier limits the object classifier data to the portion of the retinal image which contains the object. An interface controller interfaces the other elements on the integrated circuit chip with a microcontroller, which comprises a standard CPU, memory and input/output lines interfacing to the interface controller.

Claims

1. An architecture for a single-chip object classifier comprising:

a retina having an image plane upon which an image of an object to be classified is focussed, said retina organized as an array of rows and columns of pixels, each pixel containing a photosensor, outputs from said retina comprising a plurality of analog electrical signals derived from said photosensors providing a representation of said image;

position-recognizing means for identifying the portion of said image plane containing said image of said object on said retina;

object-recognizing means, responsive to said position-recognizing means, for examining a portion of output from said retina corresponding to the portion of said image plane containing said image and determining the similarity of said object to a plurality of learned classes of objects.

2. The architecture for a single-chip object classifier of claim 1, further including confidence-level generating means in said object-recognizing means, for generating a signal proportional to the degree of similarity between said object and at least one of said learned classes of objects.

3. The architecture for a single-chip object classifier of claim 1, wherein output signals from said retina are supplied to said object-recognizing means one row at a time and said position-recognizing means supplies to said object-recognizing means the row address of said pixels from said retina containing the beginning of said image.

4. The architecture for a single-chip object classifier of claim 1, further including means for interfacing to a general purpose microcontroller, such that said position-recognizing means and said object-recognizing means may be interrogated and controlled by said microcontroller.

5. The architecture for a single-chip object classifier of claim 4, further including means for generating analog voltages from the output of said microcontroller and for sending analog voltages representing selected portions of said image to said object-recognizing means.

6. The architecture for a single-chip object classifier of claim 1, further including means for performing selected image processing directly on the image plane of said retina to adapt the retinal image to a variety of illumination conditions.

7. The architecture for a single-chip object classifier of claim 1, further including velocity-determining means for performing selected image processing directly on the image plane of said retina to determine the velocity of motion of said object.

8. The architecture for a single-chip object classifier of claim 7, further including image-plane moving means, responsive to said velocity-determining means, for tracking moving objects to be classified.

9. The architecture for a single-chip object classifier of claim 4, wherein indicia in said position-recognizing means and said object-recognizing means which relate to classification of objects are readable and writable by said microcontroller.

10. An architecture for a single-chip object classifier comprising:

a retina having an image plane upon which an image of an object to be classified is focussed, said retina organized as an array of rows and columns of pixels, each of said rows identifiable by a row address, each pixel containing a photosensor, outputs from said retina comprising a plurality of analog electrical signals derived from said photosensors providing a representation of said image;

position-recognizing means for determining the row address range of said image of said object on said retina;

temporary image-storage means, responsive to said position-recognizing means, for storing the data from the ones of said pixel photosensors within said row address range of said image;

object-recognizing means, for examining the data in said temporary image storing means to determine the similarity of said object to a plurality of stored classes of objects.

11. The architecture for a single-chip object classifier of claim 10, further including means for dynamically altering said stored classes of objects.

12. The architecture for a single-chip object classifier of claim 10, further including means for interfacing to a general purpose microcontroller, such that said position-recognizing means and said object-recognizing means may be interrogated and controlled by said microcontroller.

13. The architecture for a single-chip object classifier of claim 12, further including means for generating analog voltages from the output of said microcontroller and for sending analog voltages representing a selected portion of said image to said object-recognizing means.

14. The architecture for a single-chip object classifier of claim 10, further including means for performing selected image processing directly on the image plane of said retina to adapt the retinal image to a variety of illumination conditions.

15. The architecture for a single-chip object classifier of claim 10, further including velocity-determining means for performing selected image processing directly on the image plane of said retina to determine the velocity of motion of said image.

16. The architecture for a single-chip object classifier of claim 15, further including image-plane moving means, responsive to said velocity-determining means, for tracking moving objects to be classified.

17. The architecture for a single-chip object classifier of claim 12, wherein weight patterns in said position-recognizing means and said object-recognizing means which define classes of objects are readable and writable by said microcontroller.

18. An architecture for a single-chip object classifier comprising:

a retina having an image plane upon which an image of an object to be classified is focussed, said retina organized as an array of rows and columns of pixels, each of said rows identifiable by a row address, each pixel containing a photosensor, outputs from said retina comprising a plurality of analog electrical signals derived from said photosensors providing a representation of said image;

position-recognizing means for determining the row address range of said image of said object on said retina;

temporary image-storage means, responsive to said position-recognizing means, for storing the data from the ones of said pixel photosensors within said row address range of said image;

data transfer means for transferring said data into said temporary storage means one row at a time;

object-recognizing means, for examining the data in said temporary image storing means to determine the similarity of said object to a plurality of stored classes of objects.

19. The architecture for a single-chip object classifier of claim 18, further including means for dynamically altering said stored classes of objects.

20. The architecture for a single-chip object classifier of claim 18, further including means for interfacing to a general purpose microcontroller, such that said position-recognizing means and said object-recognizing means may be interrogated and controlled by said microcontroller.

21. The architecture for a single-chip object classifier of claim 20, further including means for generating analog voltages from the output of said microcontroller and for sending analog voltages representing a selected portion of said image to said object-recognizing means.

22. The architecture for a single-chip object classifier of claim 18, further including means for performing selected image processing directly on the image plane of said retina to adapt the retinal image to a variety of illumination conditions.

23. The architecture for a single-chip object classifier of claim 18, further including velocity-determining means for performing selected image processing directly on the image plane of said retina to determine the velocity of motion of said image.

24. The architecture for a single-chip object classifier of claim 23, further including image-plane moving means, responsive to said velocity-determining means, for tracking moving objects to be classified.

25. The architecture for a single-chip object classifier of claim 20, wherein weight patterns in said position-recognizing means and said object-recognizing means which define classes of objects are readable and writable by said microcontroller.

26. The architecture for a single-chip object classifier of claim 18, wherein said object recognizing means aggregates said analog electrical signals from each row in said retina along a single wire associated therewith.

27. The architecture for a single-chip object classifier of claim 18, wherein said object recognizing means aggregates said analog electrical signals from each column in said retina along a single wire associated therewith.