Circuit arrangement and method for the regeneration and synchronization of a digital signal
First Claim
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1. A circuit arrangement for regenerating an synchronizing a high-bit-rate digital signal y.sub.(n) into a synchronized digital signal x.sub.(n), comprising:
- a variable delay line connected to the digital signal y.sub.)n) for generating a seriesof time delayed signals for each bit of said digital signal;
a correlation circuit ( 5,7 or 35,37) connected tot he digital signal y.sub.(n), the time delayed signals of the variable delay line, and to the synchronized digital data x.sub.(n), said correlation circuit generating correlation output signals representing the correlation between the synchronized data signal x.sub.(n) and the digital signal y.sub.(n) ;
at least one logic circuit (13;
55;
or
73) connected to the correlation output signals for evaluating the correlation output signals and generating a control signal which represents the middle of the eye opening between the digital signal y.sub.(n) and the synchronized digital signal x.sub.(n) ; and
a multiplexer (11) connected to the output of the logic circuit, the digital signal y.sub.(n), and the time delayed signals from the variable delay line, for generating the synchronized digital signal x.sub.(n) based upon the control signal from the logic circuit.
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Abstract
For regeneration and synchronization of a high-bit-rate digital signal, a series circuit of a controllable delay line and a decision logic is traversed by the digital signal. The decision logic contains a sampling circuit, by means of which the digital signal is sampled in the middle of its eye opening.
17 Citations
17 Claims
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1. A circuit arrangement for regenerating an synchronizing a high-bit-rate digital signal y.sub.(n) into a synchronized digital signal x.sub.(n), comprising:
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a variable delay line connected to the digital signal y.sub.)n) for generating a series of time delayed signals for each bit of said digital signal; a correlation circuit ( 5,7 or 35,37) connected tot he digital signal y.sub.(n), the time delayed signals of the variable delay line, and to the synchronized digital data x.sub.(n), said correlation circuit generating correlation output signals representing the correlation between the synchronized data signal x.sub.(n) and the digital signal y.sub.(n) ; at least one logic circuit (13;
55;
or
73) connected to the correlation output signals for evaluating the correlation output signals and generating a control signal which represents the middle of the eye opening between the digital signal y.sub.(n) and the synchronized digital signal x.sub.(n) ; anda multiplexer (11) connected to the output of the logic circuit, the digital signal y.sub.(n), and the time delayed signals from the variable delay line, for generating the synchronized digital signal x.sub.(n) based upon the control signal from the logic circuit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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17. A method of regenerating and synchronizing a high-bit-rate digital data signal y.sub.(n) into a synchronized high-bit-rate digital data signal x.sub.(n), comprising the steps of:
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receiving the high-bit-rate digital data signal y.sub.(n) and delaying said signal for each bit of said signal into a plurality of time delay signals y.sub.(n+k), where k=0, . . . , L-1, wherein n is a sampling step and L is the number of sampling values; tapping individual signals x.sub.(n) and y.sub.(y+k) from the delay line; correlating the tapped signals by discrete correlation in accordance with the equation;
##EQU3## , where N is a positive integer greater than one;
determining the maximum correlation between the signal x.sub.(n) and y.sub.(x+k) ;receiving the high-bit-rate digital signal y.sub.(n) and the tap delayed signals y.sub.(n+k) in a multiplexer; and adjusting the output of the multiplexer by the determined maximum correlation so as to generate the high-bit-rate digital data signal x.sub.(n).
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Specification