Switched row/column memory redundancy

• US 5,255,227 A
• Filed: 02/06/1991
• Issued: 10/19/1993
• Est. Priority Date: 02/06/1991
• Status: Expired due to Fees

• Current Assignee: Agilent Technologies, Inc.
• Original Assignee: Hewlett-Packard Company (HP Inc.)
• Inventors: Haeffele, Jeffrey J.
• Primary Examiner(s): LaRoche, Eugene R.
• Assistant Examiner(s): Nguyen, Viet Q.
• Application Number:
  US07/651,681
• Time in Patent Office: 986 Days
• Field of Search: 365/189.12, 365/201, 365/200, 365/203, 371/21
• US Class Current: 365/200
• CPC Class Codes: G11C 29/848 by adjacent switching

Abstract

A plurality of redundant rows/columns are added to a semiconductor memory array wherein each redundant row/column is located at a predetermined location in the memory array so as to divide the memory into equal sectors. Switches are utilized to connect the memory columns and rows and redundant memory columns and rows to row select, write circuitry, and read circuitry so that in the presence of a defective row or column, switches can be activated to remove the defective row or column from the array and to interconnect the remaining rows and columns in a predetermined adjacent pattern of interconnection. The controls for the switches comprise shift registers which are fully programmable and reprogrammable so that even through the memory array is configured to remove defective rows or columns at the point of manufacture, in the event of future defects occurring in the field, the shift registers can be reprogrammed to avoid future defective rows or columns.

Claims

1. A system for reconfiguring a memory array, said memory array having a matrix composed of a plurality of columns and a plurality of rows, row select circuitry for selectively accessing said plurality of rows, write circuitry for writing data into selected columns of said plurality of columns, and read circuitry for reading data from selected columns of said plurality of columns, said system further comprising:

a plurality of redundant columns in said memory array, each one of said plurality of redundant columns being located at a predetermined location in said memory array so as to divide said plurality of columns into equal sectors of columns,

a plurality of redundant rows in said memory array, each one of said plurality of redundant rows being located at a predetermined location in said memory array so as to divide said plurality of rows into equal sectors of rows,

means connected to said write and read circuitry for testing said plurality of columns and rows for defects, said testing means generating a reconfiguration row bit pattern when a defective row is identified and a reconfiguration column bit pattern when a defective column is identified,

a plurality of first switches connected between said row select circuitry and said plurality of rows and plurality of redundant rows, each of said first plurality of switches selectively connecting one of two of said adjacent plurality of rows and plurality of redundant rows to one row said row select circuitry,

a plurality of second switches connected between said write circuitry and said plurality of columns and plurality of redundant columns, each of said second plurality of switches selectively connecting one of two of said adjacent plurality of columns and plurality of redundant columns to one column of said write circuitry,

a plurality of third switches connected between said read circuitry and said plurality of columns and plurality of redundant columns, each of said third plurality of switches selectively connecting one of two of said adjacent plurality of columns and plurality of redundant columns to one said column read circuitry,

first means receptive of said reconfiguration row bit pattern and connected to said first plurality of switches for programmably controlling the selective connection of each said switch to said one of two adjacent rows,

second means receptive of said reconfiguration column bit pattern and connected to said second and third plurality of switches for programmably controlling the selective connection of each said switch to said one of two adjacent columns.

2. The memory array of claim 1 wherein each of said first, second, and third plurality of switches are solid state switches.

3. The memory array of claim 1 wherein each of said first and second controlling means comprises serial shift registers.

4. A system for reconfiguring a memory array, said memory array having a plurality of columns and a plurality of rows, row select circuitry for selectively accessing said plurality of rows, write circuitry for writing data into selected columns of said plurality of columns, and read circuitry for reading data from selected columns of said plurality of columns, said system further comprising:

a plurality of redundant columns in said memory array, at least one of said plurality of redundant columns being located at a predetermined location in said memory array so as to divide said plurality of columns into equal sectors of columns,

a plurality of redundant rows in said memory array, at least one of said plurality of redundant rows being located at a predetermined location in said memory array so as to divide said plurality of rows into equal sectors of rows,

a plurality of first switches connected between said row select circuitry and said plurality of rows and plurality of redundant rows, each of said first plurality of switches selectively connecting at least one of two of said adjacent plurality of rows and plurality of redundant rows to one row said row select circuitry,

a plurality of second switches connected between said write circuitry and said plurality of columns and plurality of redundant columns, each of said second plurality of switches selectively connecting at least one of two of said adjacent plurality of columns and plurality of redundant columns to one column of said write circuitry,

a plurality of third switches connected between said read circuitry and said plurality of columns and plurality of redundant columns, each of said third plurality of switches selectively connecting at least one of two of said adjacent plurality of columns and plurality of redundant columns to one said column read circuitry,

means connected to said write and read circuitry for testing said plurality of columns and rows for defects, said testing means generating a reconfiguration row bit pattern when a defective row is identified and a reconfiguration column bit pattern when a defective column is identified,

means receptive of said reconfiguration column and row bit patterns and connected to said first, second and third plurality of switches for programmably controlling the selective connection of each said switch.

5. A memory array reconfiguration system, said system comprising:

a plurality of bit lines,

a bit line circuit having a plurality of output lines with each of said output lines assigned to one of said plurality of bit lines,

a redundant bit line aligned along one side of said plurality of bit lines,

means for addressing said bit line circuit,

a plurality of switches, each one of said switches having an input connected to one of said output lines in said bit line circuit and having two switch outputs, the first of said two switch outputs being connected to the bit line corresponding to an assigned output line from said bit line circuit and the remaining one of said two switch outputs connected to an adjacent bit line, the last switch in said plurality of switches having its second switch output connected to said redundant bit line,

means connected to each of said plurality of switches for selectively controlling the operation of said switches, when any one of said plurality of bit lines is defective, said controlling means causing the switch having its first switch output connected to said defective bit line to connect the input of the aforesaid switch to its second switch output thereby connecting the adjacent bit line to the aforesaid input and disconnecting said defective bit line, said controlling means causing all remaining switches between the aforesaid switch to connect their input to their second switch outputs thereby connecting the corresponding output lines in said bit line circuit to the adjacent bit lines with the redundant bit line being connected to the last output line of said bit line circuit,

means for testing said bit line circuit for defective bit lines by addressing said addressing means with test information, said testing means delivering reconfiguration information to said controlling means for controlling the operation of each of said plurality of switches when defective bit lines are present.

6. The memory array of claim 5 wherein said switches are solid state switches.

7. The memory array of claim 5 wherein said controlling means comprises serial shift registers.

8. A memory array reconfiguration system, said system comprising:

a plurality of bit lines,

a bit line circuit having a plurality of output lines with each of said output lines assigned to one of said plurality of bit lines,

at least one redundant bit line aligned along one side of said plurality of bit lines,

means for addressing said bit line circuit,

a plurality of switches, each one of said switches having an input connected to one of said output lines in said bit line circuit and having at least two switch outputs, the first of said at least two switch outputs connected to a bit line corresponding to the assigned output line from said bit line circuit and the remaining switch outputs connected to the adjacent bit lines, the last switch in said plurality of switches having its second switch output connected to the last of said at least one redundant bit line,

means connected to each of said plurality of switches for selectively controlling the operation of said switches, when any one of said plurality of bit lines is defective, said controlling means causing the switch having its first switch output connected to said defective bit line to connect the input of the aforesaid switch to its at least one remaining switch output thereby connecting the adjacent bit line to the aforesaid output line of said bit line circuit and disconnecting said defective bit line, said controlling means causing all remaining switches between the aforesaid switch to connect their input to their at least one remaining switch output thereby connecting the corresponding output lines in said bit line circuit to the adjacent bit line with the at least one redundant bit line being connected to the last at least one output line of said bit line circuit,

means for testing said bit line circuit for defective bit lines by addressing said addressing means with test information, said testing means delivering reconfiguration information to said controlling means for controlling the operation of each of said plurality of switches when defective bit lines are present.

9. A method of reconfiguring a memory array in field equipment, said field equipment containing a microprocessor operative with said memory array, said method comprising the steps of:

providing a plurality of bit lines and a plurality of redundant bit lines in the memory array,

providing a program having test data in the microprocessor,

periodically testing the memory array for defects by having the microprocessor write test data from the program into the memory array and read data from the memory array,

identifying in the microprocessor the presence of any defective bit lines in said plurality of bit lines during the periodic test in response to the reading of the data from the memory array,

determining in the microprocessor a reconfiguration pattern for the plurality of bit lines and the plurality of redundant bit lines in response to the step of identification,

using the microprocessor to (i) switch out all defective bit lines from the tested memory array and to (ii) reconfigure the memory array around remaining good and redundant bit lines in response to the reconfiguration pattern.

10. The method of claim 9 wherein the periodic testing occurs each time the field equipment is turned on.

11. A method of reconfiguring a memory array in field equipment, said field equipment containing a microprocessor operative with said memory array, said method comprising the steps of:

providing a plurality of bit lines and a plurality of redundant bit lines in the memory array,

providing a program having test data in the microprocessor,

periodically testing the memory array by having the microprocessor write test data into the memory array and read data from the memory array,

receiving in the microprocessor the data read from the memory array,

identifying in the microprocessor the presence of any defective bit lines in said plurality of bit lines based upon said read data, if defects are present in the read data, identifying the presence of any defective bit lines in the plurality of bit lines, determining in the microprocessor a reconfiguration pattern for the plurality of bit lines and the plurality of redundant bit lines, based upon the reconfiguration pattern in the aforesaid step, switching out all defective bit lines from the tested memory array and reconfiguring the memory array around remaining good and redundant bit lines.