Semiconductor device having MOS transistor and a sidewall with a double insulator layer structure
First Claim
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1. A semiconductor device having a CMOS circuit which includes at least a P-channel MOS transistor and an N-channel MOS transistor, said semiconductor device comprising:
- a semiconductor substrate;
an isolation region formed on said semiconductor substratea P-channel MOS transistor region within said isolation region, including--an N-type well formed in the semiconductor substrate;
a first gate insulator layer formed on the semiconductor substrate;
P-type diffusion regions formed in the N-type well on both sides of the first gate insulator layer; and
a first gate electrode formed on the first gate insulator layer, said first gate electrode and said P-type diffusion regions respectively forming gate, source and drain of the P-channel MOS transistor; and
an N-channel MOS transistor region within said isolation region, including--a P-type well formed in the semiconductor substrate;
a second gate insulator layer formed on the semiconductor substrate;
N-type diffusion regions formed in the P-type well on both sides of the second gate insulator layer;
a second gate electrode formed on the second gate insulator layer, said second gate electrode having top and side surfaces, said second gate electrode and said N-type diffusion regions respectively forming gate, source and drain of the N-channel MOS transistor;
an insulating layer which covers a portion of the N-type diffusion regions, the side surfaces of the second gate electrode and at least a portion of the top surface of the second gate electrode, said insulating layer and said first gate insulator formed of identical material including nitrogen; and
a sidewall layer formed on the insulating layer to provide a smooth coverage around the side of the second gate electrode and aligning with an edge of said insulating layer over the N-type diffusion regions, a thickness of said insulating layer under said sidewall layer substantially equal to a thickness of said first gate insulator layer.
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Abstract
A semiconductor device including a semiconductor substrate with a P-type well formed in the semiconductor substrate and a gate insulator layer formed on the semiconductor substrate. N-type diffusion regions are formed in the P-type well on both sides of the gate insulator layer. A gate electrode is formed on the gate insulator layer, where the gate electrode has top and side surfaces. The gate electrode and the N-type diffusion regions respectively form gate, source and drain of a N-channel MOS transistor. An insulating layer covers a portion of the N-type diffusion regions, the side surfaces of the gate electrode and at least a portion of the top surface of the gate electrode. The side wall layer which is made of an insulating material is formed on the insulating layer to provide a smooth coverage around the side of the gate electrode and aligns with an edge of said insulating layer which stops covering the N-type diffusion regions.
58 Citations
8 Claims
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1. A semiconductor device having a CMOS circuit which includes at least a P-channel MOS transistor and an N-channel MOS transistor, said semiconductor device comprising:
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a semiconductor substrate; an isolation region formed on said semiconductor substrate a P-channel MOS transistor region within said isolation region, including-- an N-type well formed in the semiconductor substrate; a first gate insulator layer formed on the semiconductor substrate; P-type diffusion regions formed in the N-type well on both sides of the first gate insulator layer; and a first gate electrode formed on the first gate insulator layer, said first gate electrode and said P-type diffusion regions respectively forming gate, source and drain of the P-channel MOS transistor; and an N-channel MOS transistor region within said isolation region, including-- a P-type well formed in the semiconductor substrate; a second gate insulator layer formed on the semiconductor substrate; N-type diffusion regions formed in the P-type well on both sides of the second gate insulator layer; a second gate electrode formed on the second gate insulator layer, said second gate electrode having top and side surfaces, said second gate electrode and said N-type diffusion regions respectively forming gate, source and drain of the N-channel MOS transistor; an insulating layer which covers a portion of the N-type diffusion regions, the side surfaces of the second gate electrode and at least a portion of the top surface of the second gate electrode, said insulating layer and said first gate insulator formed of identical material including nitrogen; and a sidewall layer formed on the insulating layer to provide a smooth coverage around the side of the second gate electrode and aligning with an edge of said insulating layer over the N-type diffusion regions, a thickness of said insulating layer under said sidewall layer substantially equal to a thickness of said first gate insulator layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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Current AssigneeFujitsu Limited
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Original AssigneeFujitsu Limited
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InventorsSato, Noriaki
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Primary Examiner(s)CARROLL, JAMES J
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Application NumberUS07/939,433Time in Patent Office424 DaysField of Search357/23.5, 357/42, 357/43, 357/54, 357/23.9, 257/324, 257/327, 257/368, 257/369, 257/371, 257/392, 257/408, 257/410, 257/411, 257/635, 257/637-641, 257/644, 257/649, 257/650US Class Current257/637CPC Class CodesH01L 21/823842 gate conductors with differ...H01L 21/82385 gate conductors with differ...H01L 21/823864 with a particular manufactu...H01L 27/0928 comprising both N- and P- w...
