Method of manufacturing a perforated workpiece

• US 5,262,021 A
• Filed: 01/21/1993
• Issued: 11/16/1993
• Est. Priority Date: 01/29/1992
• Status: Expired due to Term

• Current Assignee: Qimonda AG (Infineon Technologies AG)
• Original Assignee: Siemens AG
• Inventors: Lehmann, Volker, Reisinger, Hans
• Primary Examiner(s): Tufariello, T. M.
• Application Number:
  US08/006,939
• Time in Patent Office: 299 Days
• Field of Search: 204/129.55, 204/129.65
• US Class Current: 205/655
• CPC Class Codes: C25F 3/12 of semiconducting materials
• CPC Class Codes: C30B 29/06 Silicon
• CPC Class Codes: C30B 33/00 After-treatment of single crystals or homogeneous polycrystalline material with defined structure C30B31/00 takes precedence
• CPC Class Codes: G02B 5/204 in which spectral selection is performed by means of a conductive grid or array, e.g. frequency selective surfaces for use with wavelengths longer than the infrared light H01Q15/0006
• CPC Class Codes: G02B 6/136 by etching
• CPC Class Codes: H01L 21/3063 Electrolytic etching

Abstract

A method of forming holes extending perpendicular to a first surface of a workpiece comprises providing the substrate wafer of n-doped, single-crystal silicon, and then electrochemically etching the substrate wafer to form a structured layer having the desired perforations. The electrochemical etching particularly occurs in a fluoride-containing electrolyte, and the substrate wafer is connected as an electrode. If the process parameters are maintained, the electrochemical etching will produce holes having a constant, substantially uniform cross section. However, varying the process parameters can cause changes in the cross section of the hole adjacent a base of the hole so that it is possible to enlarge the hole to facilitate stripping the workpiece as a lamina from the substrate.

Claims

1. A method for manufacturing a perforated workpiece having holes extending perpendicular to a first surface of the workpiece, which is of a material of n-doped, single-crystal silicon, said method comprising providing a substrate wafer of an n-doped, single-crystal silicon having the first surface, electrochemically etching the substrate to produce the structured layer by connecting the substrate as an anode, contacting the first surface of the substrate with an electrolyte, setting a current density which will influence the etching erosion, continuing the etching to form the holes extending to a desired depth and corresponding to the thickness of the finished workpiece, and then modifying the parameters of the etching process to cause an increased lateral etching to enlarge the cross section of the holes adjacent the base of the holes with this lateral etching, and subsequently stripping the structured layer of the workpiece as a lamina from the substrate wafer.

2. A method according to claim 1, wherein the electrochemical etching occurs in a fluoride-containing, acidic electrolyte.

3. A method according to claim 1, wherein the substrate wafer is a <

100>

wafer.

4. A method according to claim 1, wherein the setting of the current density is accomplished by illuminating a second surface of the substrate wafer that lies opposite the first surface.

5. A method according to claim 1, wherein the electrolyte contains hydrofluoric acid in a range of 1% to 50%.

6. A method according to claim 5, wherein the electrolyte additionally contains an oxidation agent.

7. A method according to claim 1, wherein the step of modifying the parameters includes elevating the current density to accomplish stripping of the lamina.

8. A method according to claim 1, wherein the step of modifying the parameters includes reducing the concentration of fluoride in the electrolyte to cause the stripping of the lamina.

9. A method according to claim 1, which includes, prior to etching the substrate, providing the first surface of the substrate wafer with a surface topology which defines the arrangement and location of the holes to be formed during the etching process.

10. A method according to claim 9, wherein the surface topology is composed of regularly-arranged depressions on the first surface.

11. A method according to claim 9, wherein the surface topology is produced by producing a photoresist mask on the first surface and by a subsequent alkaline etching of the first surface.

12. A method according to claim 9, wherein the surface topology is produced by electrochemical etching with an electrolyte and includes an illumination pattern being produced on the first surface upon employment of a light source having a wavelength less than 1100 nm and in that the current density in the electrolyte is set so that the anodic minority carrier current locally flows across the substrate wafer only at illuminated locations of the illuminated pattern to create an etching erosion of the first surface at these locations.

13. A method according to claim 1, which includes doping the lamina to set the conductivity of the workpiece.

14. A method according to claim 1, which includes producing one insulating layer on the surface of the lamina.

15. A method according to claim 1, wherein the perforated workpiece being produced is an optical filter.

16. A method according to claim 1, wherein the perforated workpiece being produced is a mechanical filter.