Representation and processing of hierarchical block designs
First Claim
1. In a computer aided engineering system, a method of determining at least one parameter associated with a hierarchical circuit design, the hierarchical circuit having at least one nonleaf component, the nonleaf component having at least one leaf component, and each component having at least one input port and one output port, the method comprising the steps of:
- (a) constructing a data structure representing the hierarchical circuit design, each nonleaf component of the circuit represented in the data structure by a block of data, each block of data comprising (1) a list of ports of the nonleaf component, (2) a list of components composing said nonleaf component, and (3) a partitioned list of ports of said components composing said nonleaf component, said partitioned list of ports being partitioned into classes representing nets to which said ports are connected;
(b) synthesizing, based at least upon the data structure constructed in step (a), a list of attributes associated with each block in the design;
(c) analyzing, based at least upon the list of attributes synthesized in step (b), the data structure and determining said parameter; and
(d) providing an indication of the result of step (c).
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Abstract
The disclosed invention is a method of determining one or more parameters associated with the hierarchical circuit design. The method comprises the step of: (a) constructing a data structure representing the hierarchical circuit design; (b) synthesizing a list of attributes associated with each block in the design, the synthesis starting at the lowest level nonleaf blocks in the hierarchy and proceeding through all higher level blocks in the design; and (c) based upon the list of attributes determining in the step (b), analyzing the data structure and determining the parameter. One of the parameters determined is the delay associated with each leaf component.
33 Citations
43 Claims
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1. In a computer aided engineering system, a method of determining at least one parameter associated with a hierarchical circuit design, the hierarchical circuit having at least one nonleaf component, the nonleaf component having at least one leaf component, and each component having at least one input port and one output port, the method comprising the steps of:
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(a) constructing a data structure representing the hierarchical circuit design, each nonleaf component of the circuit represented in the data structure by a block of data, each block of data comprising (1) a list of ports of the nonleaf component, (2) a list of components composing said nonleaf component, and (3) a partitioned list of ports of said components composing said nonleaf component, said partitioned list of ports being partitioned into classes representing nets to which said ports are connected; (b) synthesizing, based at least upon the data structure constructed in step (a), a list of attributes associated with each block in the design; (c) analyzing, based at least upon the list of attributes synthesized in step (b), the data structure and determining said parameter; and (d) providing an indication of the result of step (c). - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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17. In a computer aided engineering system, a method of determining at least one parameter associated with a hierarchical circuit design, the hierarchical circuit having at least one nonleaf component, the nonleaf component having at least one leaf component, and each component having at least one input port and one output port, the method comprising the steps of:
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(a) constructing a data structure representing the hierarchical circuit design, each nonleaf component of the circuit represented in the data structure by a block of data, each block of data comprising (1) a list of ports of the nonleaf component, (2) a list of components composing said nonleaf component, and (3) a partitioned list of ports of said components composing said nonleaf component, said partitioned list of ports being partitioned into classes representing nets to which said ports are connected; (b) synthesizing, based at least upon the data structure constructed in step (a), a list of attributes associated with each block in the design, the synthesis comprising; (i) determining a gate count ("GL ") for each leaf component represented in the data structure; (ii) calculating a gate count ("GNL ") for each nonleaf component represented in the data structure; (iii) determining a connection count ("NL ") and pin capacitance ("CL ") for each port of each leaf component represented in the data structure; (iv) calculating a connection count ("NNL ") and pin capacitance ("CNL ") for each net represented in the data structure; (v) determining a connection count ("NNPL ") and pin capacitance ("CNLP ") for each port of each nonleaf component represented in the data structure; (vi) determining an intrinsic capacitance ("I") for each net represented in the data structure; and (vii) determining a total capacitance ("T") for each net represented in the data structure; (c) analyzing, based at least upon the list of attributes synthesized in step (b), the data structure and determining said parameter; and (d) providing an indication of the result of step (c). - View Dependent Claims (18, 19, 20, 21, 22, 23, 24, 25, 26)
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27. In a computer aided engineering system, a method of determining a delay parameter associated with a hierarchical circuit design, the hierarchical circuit having at least one nonleaf component, the nonleaf component having at least one leaf component, and each component having at least one input port and one output port, the method comprising the steps of:
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(a) constructing a data structure representing the hierarchical circuit design, each nonleaf component of the circuit represented in the data structure by a block of data, each block of data comprising (1) a list of ports of the nonleaf component, (2) a list of components composing said nonleaf component, and (3) a partitioned list of ports of said components composing said nonleaf component, said partitioned list of ports being partitioned into classes representing nets to which said ports are connected; (b) synthesizing, based at least upon the data structure constructed in step (a), a list of attributes associated with each block in the design; (c) analyzing, based at least upon the list of attributes synthesized in step (b), the data structure and determining said delay parameter, the analysis comprising; (i) determining an attribute ("T") associated with each port of each nonleaf component represented by the data structure; and (ii) determining the attribute T associated with each net and port represented in the data structure; and (d) providing an indication of the result of step (c). - View Dependent Claims (28, 29, 30)
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31. In a computer aided engineering system, a method of determining a delay parameter associated with a hierarchical circuit design, the hierarchical circuit having at least one nonleaf component, the nonleaf component having at least one leaf component, and each component having at least one input port and one output port, the method comprising the steps of:
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(a) constructing a data structure representing the hierarchical circuit design, each nonleaf component of the circuit represented in the data structure by a block of data, each block of data comprising (1) a list of ports of the nonleaf component, (2) a list of components composing said nonleaf component, and (3) a partitioned list of ports of said components composing said nonleaf component, said partitioned list of ports being partitioned into classes representing nets to which said ports are connected; (b) synthesizing, based at least upon the data structure constructed in step (a), a list of attributes associated with each block in the design, the synthesis comprising; (i) determining a gate count ("GL ") for each leaf component represented in the data structure; (ii) calculating a gate count ("GNL ") for each nonleaf component represented in the data (iii) determining a connection count ("NL ") and pin capacitance ("CL ") for each port of each leaf component represented in the data structure; (iv) calculating a connection count ("NNL ") and pin capacitance ("CNLP ") for each net represented in the data structure; (v) determining a connection count ("NNPL ") and pin capacitance ("CNLP ") for each port of each nonleaf component represented in the data structure; (vi) determining an intrinsic capacitance ("I") for each net represented in the data structure; and (vii) determining a total capacitance ("T") for each net represented in the data structure; (c) analyzing, based at least upon the list of attributes synthesized in step (b), the data structure and determining said delay parameter, the analysis comprising; (i) determining an attribute ("T") associated with each port of each nonleaf component represented by the data structure; and (ii) determining the attribute T associated with each net and port represented in the data structure; and (d) providing an indication of the result of step (c). - View Dependent Claims (32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43)
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Specification