Large scale integrated circuit for low voltage operation

• US 5,262,999 A
• Filed: 03/24/1992
• Issued: 11/16/1993
• Est. Priority Date: 06/17/1988
• Status: Expired due to Term

• Current Assignee: Hitachi, Ltd., Hitachi Vlsi Engineering Corporation
• Original Assignee: Hitachi, Ltd., Hitachi Vlsi Engineering Corporation
• Inventors: Itoh, Kiyoo, Tanaka, Hitoshi, Nakagome, Yoshinobu, Kawajiri, Yoshiki, Etoh, Jun, Kume, Eiji
• Primary Examiner(s): Bowler, Alyssa H.
• Application Number:
  US07/838,505
• Time in Patent Office: 602 Days
• Field of Search: 365/203, 365/226, 365/227, 365/228, 365/229, 365/189.09, 365/189.11, 307/296.1, 307/296.6, 307/296.8
• US Class Current: 365/226
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence

Abstract

Disclosed is a one-chip ULSI which can carry out the fixed operation in a wide range of power supply voltage (1 V to 5.5 V). This one-chip ULSI is composed of a voltage converter circuit(s) which serves to a fixed internal voltage for a wide range of power supply voltage, an input/output buffer which can be adapted to several input/output levels, a dynamid RAM(s) which can operate at a power supply voltage of 2 V or less, etc. This one-chip ULSI can be applied to compact and portable electronic devices such as a lap-top type personal computer, an electronic pocket note book, a solid-state camera, etc.

Claims

1. A semiconductor device comprising:

a plurality of data lines, a plurality of word lines intersecting them, memory cells located at the intersecting points, and sense amplifiers each for amplifying a memory cell signal read out on each of the data lines;

each of said memory cells comprising a switching means which is controlled by a voltage on each of the word lines, and a capacitor having at last two terminals for signal storage, and one of the terminals of the capacitor being connected with each of the data lines through the switching means and another terminal connected with a first control signal line; and

a maximum voltage amplitude of said first control signal line being larger than that of said data lines, wherein a potential of each of said data lines is amplified to an amplitude of 2V or less for a memory read or write operation, and the potential of each of said data lines is precharged at an intermediate level between high and low levels of the voltage amplitude during a stand-by period for said read or write operation.

2. A semiconductor device according to claim 1, wherein said plurality of data lines, plurality of word lines, memory cells, and sense amplifiers comprise a memory.

3. A semiconductor device according to claim 2, wherein each of the sense amplifiers comprises a plurality of metal-oxide-semiconductor field effect transistors commonly known as MOS-FETs and each of the MOS-FETs has a threshold voltage which is lower than 1/3 of said voltage amplitude of the data lines.

4. A semiconductor device according to claim 2, wherein the potential on a low potential side in the voltage amplitude of the data lines is higher than the potential on a low potential side of the word lines by a voltage amplitude amount of at least as much as said first control signal line.

5. A semiconductor device according to claim 2, wherein the amount of signals on a high potential side stored in said memory cell is more than that on a low potential side.

6. A semiconductor device according to claim 2, wherein the potential of said first control signal line during the stand-by period of the memory is located between the signal potential of the memory cell signal on the high potential side and that one the low potential side.

7. A semiconductor device according to claim 2, wherein the memory cell signals are read out on the data lines by varying the potential of said first control signal line from its high level to its low level.

8. A semiconductor device according to claim 2, further comprising common driving lines for said sense amplifiers, wherein when the sense amplifiers start to operate, the voltage amplitude of the common driving lines for said sense amplifiers is made larger than the voltage amplitude of the data lines.

9. A semiconductor device according to claim 2 further comprising:

common driving lines for driving said sense amplifiers; and

boosting capacitors provided for the same amplifiers;

wherein the voltage amplitude of the common driving lines for said sense amplifiers when the sense amplifiers start to operate is made larger than the voltage amplitude of the data lines.

10. A semiconductor device according to claim 2 further comprising:

common drive lines for driving said means amplifiers, wherein power supplies having at least two kinds of different power supply voltages are connected with said common driving lines through switches and said switches are switched so that the voltage amplitude of the common driving lines of said sense amplifiers when the sense amplifiers start to operate is larger than the voltage amplitude of the data lines.

11. A semiconductor device according to claim 10, wherein at least one of said two kids of power supplies provides a maximum value or minimum value of the voltage on the data lines.

12. A semiconductor device according to claim 1, wherein each of the same amplifiers comprises a plurality of metal-oxide-semiconductor field effect transistors (MOS-FETs) and each of the MOS-FETs has a threshold voltage which is lower than 1/3 of said voltage amplitude of the data lines.

13. A semiconductor device according to claim 1, wherein the potential on the lower potential side in the voltage amplitude of the data lines is higher than the potential on the low potential side of the word lines by the voltage amplitude of said first control signal lines or more.

14. A semiconductor device according to claim 1, wherein the amount of signals on a high potential side stored in said memory cell is more than that on a low potential side.

15. A semiconductor device according to claim 1, wherein the potential of said first control signal line during the stand-by period of the memory is located between the signal potential of the memory cell signal on a high potential side of the memory cell and that on low potential side of the memory cell.

16. A semiconductor device according to claim 1, wherein the memory cell signals are read out on the data lines by varying the potential of said first control signal line from its high level to its low level.

17. A semiconductor device according to claim 1, wherein the voltage amplitude of a common driving line for said sense amplifiers when the sense amplifiers start to operate is made larger than the voltage amplitude of the data lines.

18. A semiconductor device according to claim 1 further comprising:

common driving lines for driving said sense amplifiers; and

boosting capacitors provided for the sense amplifiers;

wherein the voltage amplitude of the common driving lines for said sense amplifiers when the sense amplifiers start to operate is made larger than the voltage amplitude of the data lines.

19. A semiconductor device according to claim 1 further comprising:

common driving lines for driving said sense amplifiers, wherein power supplies having at least two kinds of different power supply voltages are connected with said common driving lines through switches and said switches are switched so that the voltage amplitude of the common driving lines of said sense amplifiers when the sense amplifiers start to operate is larger than the voltage amplitude of the data lines.

20. A semiconductor device according to claim 9, wherein at least one of said two kinds of power supplies provides one of a maximum value and a minimum value of the voltage on the data lines.

21. A semiconductor device according to claim 1 further including:

a power supply voltage generated inside a chip which is independent of a power supply voltage outside the chip being used as a voltage for precharging the common driving lines for said sense amplifiers and said data lines.

22. A semiconductor device according to claim 21, wherein the value of said power supply voltage generated inside the chip is substantially an intermediate value between a maximum voltage and a minimum voltage when the power supply voltage outside the chip is higher than a certain voltage whereas the difference between it and one of the maximum and minimum voltage is made constant.

23. A semiconductor device according to claim 21, wherein when said sense amplifiers start to operate, the voltage of the data lines is varied to effectively boost the absolute value of the gate-source voltage of transistors in each of the sense amplifiers.

24. A semiconductor device according to claim 23, wherein said voltage on the data lines is statically or dynamically boosted by boosting transistors or boosting capacitors.

25. A semiconductor device according to claim 1, wherein said sense amplifiers operate with the voltage amplitude higher then that of the data lines and such of said means amplifiers includes an inverter which operates with the same voltage amplitude as that of the data lines.

26. A semiconductor device according to claim 2, wherein the threshold voltage of the transistors in each of the same amplifiers is varied in accordance with the operation voltage of the sense amplifiers.

27. A semiconductor device according to claim 26, wherein said threshold voltage is varied through dynamic circuit operation.

28. A semiconductor device according to claim 27, wherein said threshold voltage is varied in a range including 0 V.

29. A semiconductor device according to claim 27, wherein said threshold voltage is varied by varying a substrate voltage.