Multiple bus architecture for flexible communication among processor modules and memory subsystems and specialized subsystems

• US 5,263,139 A
• Filed: 05/19/1992
• Issued: 11/16/1993
• Est. Priority Date: 05/19/1992
• Status: Expired due to Term

• Current Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Bechtolsheim, Andreas, Testa, James
• Primary Examiner(s): Fleming, Michael R.
• Assistant Examiner(s): Sheikh, Ayaz R.
• Application Number:
  US07/886,045
• Time in Patent Office: 546 Days
• Field of Search: 395/325, 395/275, 395/425, 395/725, 361/42
• US Class Current: 710/307
• CPC Class Codes: G06F 13/14 Handling requests for interconnection or transfer
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence

Abstract

A multiple bus architecture for flexible communication between processors, memory subsystems, and specialized subsystems over multiple high performance communication pathways. The multiple bus architecture enables flexible communication between processors and devices coupled to a multiprocessor bus, a system interconnect bus, an external bus, an input/output bus, and a memory subsystem. Processor modules coupled to multiprocessor bus slots access the memory subsystem over the multiprocessor bus. System interconnect modules coupled to system interconnect bus slots access the memory subsystem via the system interconnect bus, and the multiprocessor bus. Processor modules coupled to multiprocessor bus slots access devices on the external bus via the system interconnect bus.

Claims

1. A multiple bus architecture for a computer system, comprising:

memory bus for communicating with a memory subsystem, the memory bus having a first bandwidth defined by a first bit width and a first data frequency, the memory subsystem having a main memory, and a video memory;

multiprocessor bus for communicating with at least one processor module the multiprocessor bus having a second bandwidth substantially equal to the first bandwidth, the second bandwidth defined by a second bit width and a second data frequency, such that the first bit width equals twice the second bit width and the second data frequency equals twice the first data frequency;

memory controller means coupled to communicate over the memory bus and the multiprocessor bus, the memory controller means receiving access requests from the processor modules over the multiprocessor bus and accessing the memory subsystem in accordance with the access requests;

system interconnect bus for communicating with at least one system interconnect module, and at least one input/output device;

first bus interface means coupled to communicate over the multiprocessor bus and the system interconnect bus, the first bus interface means translating access requests between the multiprocessor bus and the system interconnect bus, such that the system interconnect modules communicate with the memory subsystem over the system interconnect bus and the multiprocessor bus and the memory bus.

2. The multiple bus architecture of claim 1, further comprising:

an external bus for communication with a plurality of peripheral devices;

second bus interface means coupled to communicated over the system interconnect bus and the external bus, such that the second bus interface means receives an access request over the system interconnect bus, and accesses the peripheral devices in accordance with the access request over the system interconnect bus.

3. The multiple bus architecture of claim 1, wherein the main memory subsystem comprises a plurality of SIMM memory modules coupled for communication over the memory bus.

4. The multiple bus architecture of claim 1, wherein the main memory comprises at least one DRAM module coupled for communication over the memory bus.

5. The multiple bus architecture of claim 4, wherein the main memory further comprises at least one SRAM module coupled for communication over the memory bus.

6. The multiple bus architecture of claim 1, wherein the video memory comprises at least one VRAM module coupled for communication over the memory bus.

7. The multiple bus architecture of claim 6, further comprising video connector means coupled for communication over a video bus of the VRAM modules, the video connector means for transmitting video signals to a display device.

8. A method for communication in a computer system having a multiple bus architecture, comprising the steps of:

receiving a first access request from a processor module over a multiprocessor bus according to a first bandwidth defined by a first data frequency and a first bit width, the first access request targeted for a memory subsystem comprising a main memory and a video memory;

translating the first access request into a corresponding first access of the memory subsystem over the memory bus according to a second bandwidth substantially equal to the first bandwidth, the second bandwidth defined by a second data frequency and a second bit width, such that the second bit width equals twice the first bit width and the first data frequency equals twice the second data frequency;

receiving a second access request over a system interconnect bus, the second access request targeted for the memory subsystem;

translating the second access request into a third access request over the multiprocessor bus targeted for the memory subsystem;

translating the third access request into a corresponding second access of the memory subsystem over the memory bus.

9. The method of claim 8, further comprising the steps of:

receiving a fourth access request over the multiprocessor bus, the fourth access request targeted for a device coupled to an external bus;

translating the fourth access request into a fifth access request over the system interconnect bus targeted for the device;

translating the fifth access request into a corresponding access of the device over the external bus.

10. The method of claim 8, wherein the memory subsystem comprises a plurality of SIMM memory modules coupled to the memory bus.

11. The method of claim 8, wherein the memory subsystem comprises at least one DRAM module coupled to the memory bus.

12. The method of claim 11, wherein the memory subsystem further comprises at least one SRAM module coupled to the memory bus.

13. The method of claim 11, wherein the memory subsystem further comprises at least one VRAM module coupled to the memory bus.