Digital controlled inverter and method

• US 5,272,615 A
• Filed: 05/01/1992
• Issued: 12/21/1993
• Est. Priority Date: 05/01/1992
• Status: Expired due to Fees

• Current Assignee: Engineered Magnetics, Inc.
• Original Assignee: Engineered Magnetics, Inc.
• Inventors: Wert, Harry E.
• Primary Examiner(s): BEHA JR, WILLIAM
• Application Number:
  US07/877,482
• Time in Patent Office: 599 Days
• Field of Search: 363/25, 363/26, 363/41, 363/42, 363/56, 363/79, 363/80, 363/97
• US Class Current: 363/41
• CPC Class Codes: H02M 7/48 using discharge tubes with control electrode or semiconductor devices with control electrode

Abstract

A digital controlled inverter (100) for inverting an input signal to an alternating current signal having a clock generator (104) for generating a high frequency clock timing signal and a latch (106) for controlling the passage of the clock timing signal to a power stage (102). The power stage (102), which provides a low distortion alternating current signal, is controlled by the latch (106). A control loop (108) is provided for sensing and converting the alternating current signal to a command signal. The command signal controls the state of the latch (106). The latch (106) is reset at the rate of the clock timing signal and updated with the command signal to provide pulse-to-pulse regulation of the alternating current signal. The inverter (100) comprises a transient response to variations in load proportional to the clock timing signal. In a preferred embodiment, the latch (106) functions as a switch for controlling the power output stage (102). The control loop (108) serves to provide the command signal to operate the latch (106). The alternating current signal is rectified and converted to a digital word and then compared to a reference digital word in a digital comparator (138) to provide the command signal to the latch (106).

Claims

1. A digital controlled inverter comprising:

signal;

latching means for controlling the passage of said clock timing signal to an output stage;

power means located within said output stage for providing a low distortion alternating current signal, said power means controlled by said latching means; and

control loop means for sensing and converting said alternating current signal to a command signal,

wherein said command signal controls the state of said latching means, said latching means being reset at the rate of said clock timing signal and updated with said command signal to provide pulse-to-pulse regulation of said alternating current signal, said inverter comprising a transient response to variations in load proportional to said clock timing signal.

2. The digital controlled inverter of claim 1 wherein said generating means includes a clock pulse generator.

3. The digital controlled inverter of claim 1 wherein said latching means includes a latch.

4. The digital controlled inverter of claim 1 wherein said power means includes an electronic power output stage.

5. The digital controlled inverter of claim 1 wherein said control loop means includes a voltage feedback circuit to sense and convert said alternating current signal to a direct current signal.

6. The digital controlled inverter of claim 1 wherein said control loop means includes a current feedback circuit to sense and convert said alternating current signal to a constant current direct current signal

7. The digital controlled inverter of claim 1 wherein said control loop means includes an analog-to-digital converter for converting a direct current signal to an equivalent digital signal.

8. The digital controlled inverter of claim 1 wherein said control loop means includes a read-only memory device for providing a digital word reference.

9. The digital controlled inverter of claim 1 wherein said control loop means comprises a comparator for generating said command signal.

10. The digital controlled inverter of claim 1 further including a buffer driver circuit to amplify said command signal received from said latching means.

11. The digital controlled inverter of claim 1 further including a transformer magnetic for isolating said power means from an output terminal.

12. The digital controlled inverter of claim 1 further including a low pass filter for removing harmonic components from said alternating current signal.

13. The digital controlled inverter of claim 1 further including an electromagnetic interference filter for blocking high frequency noise generated by said generating means from entering an input power line.

14. The digital controlled inverter of claim 1 further including an over-current circuit for sensing and terminating an over-current condition.

15. The digital controlled inverter of claim 1 further including a driver shutdown circuit for disconnecting said power means in response to an overcurrent condition.

16. A digital controlled inverter comprising:

a clock generator for generating a high frequency clock timing signal;

a latch for controlling the passage of said clock timing signal to an output stage;

power means located within said output stage for providing a low distortion alternating current signal, said power means controlled by said latch; and

control loop means for sensing and converting said alternating current signal to a command signal,

wherein said command signal controls the state of said latch, said latch being reset at the rate of said clock timing signal and updated with said command signal to provide pulse-to-pulse regulation of said alternating current signal, said inverter comprising a transient response to variations in load proportional to said clock timing signal.

17. A method for providing digital controlled inversion of an input signal to an alternating current signal, said method comprising the steps of:

generating a high frequency clock timing signal;

controlling the passage of said clock timing signal to an output stage;

providing a low distortion alternating current signal from said output stage controlled by a latch;

sensing and converting said alternating current signal to a command signal;

latching said command signal and controlling the state of said latch with said command signal;

resetting said latch at the rate of said clock timing signal;

updating said latch with said command signal to provide pulse-to-pulse regulation of said alternating current signal; and

providing a transient response to variations in load proportional to said clock timing signal.

18. The method of claim 17 further including the step of isolating said output stage from an output terminal with a transformer magnetic.

19. The method of claim 17 further including the step of filtering said alternating current signal to remove harmonic components.

20. The method of claim 17 further including the step of sensing and terminating an over-current condition with an over-current circuit.