Spread spectrum communication system

• US 5,280,499 A
• Filed: 10/16/1992
• Issued: 01/18/1994
• Est. Priority Date: 10/18/1991
• Status: Expired due to Fees

• Current Assignee: Ricoh Company Limited
• Original Assignee: Ricoh Company Limited
• Inventors: Suzuki, Masamitsu
• Primary Examiner(s): Barron, Jr., Gilberto
• Application Number:
  US07/962,348
• Time in Patent Office: 459 Days
• Field of Search: 375/1
• US Class Current: 375/151
• CPC Class Codes: H04B 1/707 using direct sequence modulation

Abstract

A spread spectrum communication system includes a transmitter having: a data generator for generating a data signal; a pn generator for generating a first pn signal in accordance with a pn code clock; a modulator for modulating the pn code clock by synchronizing the data signal with a multiple N of one period of the first pn signal; a first part for detecting one period of the first pn signal; a second part for outputting a clock to the data generator in accordance with a converted period equal to a multiple N of the detected period; and an output part for transmitting a signal at an output of the pn generator, and a receiver which receives the transmitted signal, the receiver having: a second pn generator for generating a second pn signal in synchronism with the transmitted signal; a demodulator for demodulating the transmitted signal with the second pn signal; a third part for detecting one period of the second pn signal; a fourth part for outputting a timing signal in accordance with a converted period equal to a multiple N of the detected period; and a discriminator for detecting each bit of a demodulated signal in synchronism with the timing signal.

Claims

1. A spread spectrum communications system comprising:

a transmitter including;

data generating means for generating a data signal to be transmitted;

pn generating means for generating a first pn code sequence in accordance with a pn code clock;

modulation means for modulating said pn code clock in accordance with said data signal by synchronizing said data signal with a multiple N of one period of said first pn code sequence;

first means for detecting one period of said first pn code sequence generated by said pn generating means;

second means for converting said detected period of said first pn code sequence into a period equal to a multiple N of said detected period and for outputting a clock with said N period to said data generating means; and

output means for transmitting a signal produced at an output of said pn generating means, and

a receiver which receives the transmitted signal from the transmitter, said receiver including;

second pn generating means for generating a second pn code sequence in synchronism with said transmitted signal;

demodulation means for demodulating said transmitted signal with said second pn code sequence generated by said second pn generating means so as to reproduce data corresponding to said data signal;

third means for detecting one period of said second pn code sequence;

fourth means for converting said detected period of said second pn code sequence into a period equal to a multiple N of said detected period and for outputting a timing signal in accordance with said N period; and

discrimination means for detecting whether each bit of a demodulated signal at an output of said demodulation means is equal to a high value "1" or a low value "0" in synchronism with said timing signal of said fourth means.

2. A spread spectrum communication system according to claim 1, wherein said first means and said second means of said transmitter include a counter for counting a prescribed number D of bits of said pn code clock, said number D of the bits corresponding to one period of said data signal generated by said data generating means.

3. A spread spectrum communication system according to claim 1, wherein said pn generating means of said transmitter includes a shift register for generating a plurality of bits of the first pn code sequence at an output of said shift register, said first pn code sequence being formed of a maximal-length linear shift register sequence, and wherein said first means includes a comparator having a plurality of reference bits formed of a prescribed bit pattern, so that the bits of the first pn code sequence of said shift register are compared with the reference bits of said comparator and a detect signal indicating one period of the first pn code sequence is output to said second means.

4. A spread spectrum communication system according to claim 1, wherein said third means and said fourth means of said receiver are made up of a counter and a decoder, said counter counting a prescribed number D of bits of a second pn code clock generated at said receiver in accordance with said transmitted signal, said number D of said bits being equal to a multiple N of the detected period of the second pn code sequence, so that said counter outputs a detect signal to said decoder each time the number D of bits of the second pn code clock is counted, and said decoder outputting a timing signal to said discrimination means at a timing corresponding to the center of each bit of the demodulated signal.

5. A spread spectrum communication system according to claim 1, wherein said second pn generating means of said receiver includes a shift register for generating a plurality of bits of the second pn code sequence at an output of said shift register, said second pn code sequence being formed of a maximal-length linear shift register sequence, and wherein said third means includes a comparator having a plurality of reference bits formed of a prescribed bit pattern, so that the bits of the second pn code sequence of said shift register are compared with the reference bits of said comparator and a detect signal indicating one period of the second pn code sequence is output by said comparator to said fourth means.

6. A spread spectrum communication system according to claim 1, wherein said discrimination means of said receiver is made up of a timing discriminator and a bit timing generator, said bit timing generator generating a bit timing signal at a timing corresponding to a start of each bit of the data signal relative to a central frequency of the first pn code sequence at the transmitter, said timing discriminator being coupled to said fourth means and detecting whether each bit of a signal at an output of said fourth means is equal to the high value "1" or the low value "0" by detecting whether said signal at the output of the fourth means has an advance or delay relative to the bit timing signal of said bit timing generator.

7. A spread spectrum communication system according to claim 6, wherein said third means and said fourth means of said receiver include a counter for counting a prescribed number D of bits of a second pn code clock generated at said receiver in accordance with said transmitted signal, said number D of the bits corresponding to one period of said data signal generated by said data generating means.

8. A spread spectrum communication system according to claim 6, wherein said second pn generating means of said receiver includes a shift register for generating a plurality of bits of the second pn code sequence at an output of said shift register, said second pn code sequence being formed of a maximal-length linear shift register sequence, and wherein said third means includes a comparator having a plurality of reference bits formed of a prescribed bit pattern, so that the bits of the second pn code sequence of said shift register are compared with the reference bits of said comparator and a detect signal indicating one period of the second pn code sequence is output by said comparator to said fourth means.

9. A spread spectrum communication system according to claim 1, further comprising a bit timing generator and a bit counter, said bit timing generator being connected to said fourth means when a preamble is received from said transmitter prior to reception of the transmitted signal, and said bit counter being connected to said discrimination means during the receiving of said preamble, wherein said bit counter counts a prescribed number N of receptions of either of values "1" and "0" corresponding to the preamble which values are detected by said discrimination means, so as to detect a separator of the transmitted signal, and wherein said bit timing generator generates a detect signal after said separator of the transmitted signal is detected, and said bit timing generator supplying an output signal of said fourth means to said discrimination means at a timing corresponding to a start of one period of the second pn code sequence, and wherein said bit timing generator supplies only the (M+1)-th output signal of the fourth means to the discrimination means when said number N is an odd number (N=2M+1, M≧

1).

10. A spread spectrum communication system according to claim 9, wherein said second pn generating means of said receiver includes a shift register for generating a plurality of bits of the second pn code sequence at an output of said shift register, said second pn code sequence being formed of a maximal-length linear shift register sequence, and wherein said third means includes a comparator having a plurality of reference bits formed of a prescribed bit pattern, so that the bits of the second pn code sequence of said shift register are compared with the reference bits of said comparator and a detect signal indicating one period of the second pn code sequence is output by said comparator to said fourth means.

11. A spread spectrum communication system according to claim 9, wherein, when said number N is an even number, said third means and said fourth means are made up of two decoders so that said timing signal is output by one of the decoders to said discrimination means at a timing corresponding to the center of each bit of the second pn code sequence.

12. A spread spectrum communication system according to claim 10, wherein, when said number N is an even number, said third means and said fourth means are made up of two comparators so that said timing signal is output by one of the comparators to said discrimination means at a timing corresponding to the center of each bit of the second pn code sequence.