Circuit and method of controlling a VCO with capacitive loads

• US 5,281,927 A
• Filed: 05/20/1993
• Issued: 01/25/1994
• Est. Priority Date: 05/20/1993
• Status: Expired due to Fees

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Codex Corporation
• Inventors: Parker, Lanny L.
• Primary Examiner(s): Pascal, Robert J.
• Assistant Examiner(s): Kinkead, Arnold M.
• Application Number:
  US08/064,311
• Time in Patent Office: 250 Days
• Field of Search: 331/1 A, 331/1 R, 331/34, 331/25, 331/10, 331/11, 331/57, 328/155, 307/262, 307/523, 307/525, 307/528, 307/511
• US Class Current: 331/1.00A
• CPC Class Codes: H03K 5/133 using a chain of active delay devices
• CPC Class Codes: H03L 7/0995 the oscillator comprising a ring oscillator
• CPC Class Codes: H03L 7/191 using at least two different signals from the frequency divider or the counter for determining the time difference H03L7/193, H03L7/195 take precedence

Abstract

A phase lock loop operates independent of temperature and process variation by digitally loading a VCO until reaching the desired operating frequency. The VCO reaches a high output frequency even under worst case processing by controlling multiple current mirrors to increase inverter switching current without slowing the response of the VCO to changes in loop node voltage. An Initialize-to-VDD circuit sets the loop node voltage to V_DD so that the load control circuit need only increase loading to slow down the VCO to the desired operating frequency. A frequency range detector monitors the output frequency of the VCO and passes control signals to a load control circuit to activate digital loads and slow down the VCO to the desired operating frequency.

Claims

1. A circuit for controlling an output signal frequency of a voltage controlled oscillator (VCO), comprising:

first means operating in response to the output signal frequency of the VCO for providing a first control signal having a first logic state upon detecting the VCO operating above a predetermined frequency;

a shift register operating in response to said first state of the first control signal for rotating a first logic state between a plurality of outputs;

a first control circuit responsive to said first logic state from a first one of said plurality of outputs of said shift register and said first logic state of said first control signal for providing a first enable signal;

a first counter having an enable input and a plurality of outputs, said enable input receiving said first enable signal, said plurality of outputs providing a first digital value which increments at each first enable signal; and

a load circuit having a first output coupled to an output of the VCO and operating in response to said first digital value applied at a first control input for slowing the output signal frequency of the VCO.

2. The circuit of claim 1 wherein said first control circuit includes a first AND gate having first and second inputs and an output, said first input being coupled to said first one of said plurality of outputs of said shift register, said second input receiving said first logic state of said first control signal, said output providing said first enable signal.

3. The circuit of claim 2 wherein the VCO includes:

a first inverter having an input, an output and a control input, said control input receiving a loop node voltage for controlling the output signal frequency of the VCO;

a second inverter having an input coupled to said output of said first inverter and having an output; and

a third inverter having an input coupled to said output of said second inverter and having an output for providing the output signal frequency of the VCO, said output being coupled to said input of said first inverter.

4. The circuit of claim 3 wherein said load circuit includes a second output coupled to said output of said second inverter and a third output coupled to said output of said first inverter.

5. The circuit of claim 4 further comprising:

a second control circuit responsive to said first logic state from a second one of said plurality of outputs of said shift register and said first logic state of said first control signal for providing a second enable signal; and

a second counter having an enable input and a plurality of outputs coupled to a second control input of said load circuit, said enable input receiving said second enable signal, said plurality of outputs providing a second digital value which increments at each second enable signal to increase loading on said second inverter.

6. The circuit of claim 5 further comprising:

a third control circuit responsive to said first logic state from a third one of said plurality of outputs of said shift register and said first logic state of said first control signal for providing a third enable signal; and

a third counter having an enable input and a plurality of outputs coupled to a third control input of said load circuit, said enable input receiving said third enable signal, said plurality of outputs providing a third digital value which increments at each third enable signal to increase loading on said first inverter.

7. The circuit of claim 6 wherein said second control circuit includes a second AND gate having first and second inputs and an output, said first input being coupled to said second one of said plurality of outputs of said shift register, said second input receiving said first logic state of said first control signal, said output providing said second enable signal.

8. The circuit of claim 7 wherein said third control circuit includes a third AND gate having first and second inputs and an output, said first input being coupled to said third one of said plurality of outputs of said shift register, said second input receiving said first logic state of said first control signal, said output providing said third enable signal.

9. A method of controlling an output signal frequency of a voltage controlled oscillator (VCO), comprising the steps of:

providing a first control signal having a first logic state upon detecting the VCO operating above a predetermined frequency;

rotating a first logic state between a plurality of outputs of a shift register in response to said first state of said first control signal;

providing a first enable signal in response to said first logic state from a first one of said plurality of outputs of said shift register and said first logic state of said first control signal;

incrementing a first digital value at a plurality of outputs of a first counter upon receiving said first enable signal; and

loading an output of the VCO in response to said first digital value for slowing the output signal frequency of the VCO.

10. An integrated phase lock loop, comprising:

first means for comparing a phase difference of first and second input signals and generating an output signal to charge and discharge a loop node;

second means having an output coupled to said loop node and operating in response to the first input signal for initializing said loop node to a predetermined voltage;

a VCO having an input coupled for receiving said output signal of said first means and having an output for providing an oscillator signal;

third means for dividing down said oscillator signal into first and second divided oscillator signals, sa-;

d first divided oscillator signal operating as said second input signal of said first means;

fourth means coupled for receiving said second divided oscillator signal and said first input, signal and generating a first control signal when said second, divided oscillator signal changes logic state more than a predetermined number of times during a first logic state of said first input signal;

a shift register operating in response to said first state of said first control signal for rotating a first logic state between a plurality of outputs;

a first control circuit responsive to said first logic state from a first one of said plurality of outputs of said shift register and said first logic state of said first control signal for providing a first enable signal;

a first counter having an enable input and a plurality of outputs, said enable input receiving said first enable signal, said plurality of outputs providing a first digital value which increments at each first enable signal; and

a load circuit having a first output coupled to said output of said VCO and operating in response to said first digital value applied at a first control input to increase loading at said output of said VCO.

11. The phase lock loop of claim 10 wherein said first control circuit includes a first AND gate having first and second inputs and an output, said first input being coupled to said first one of said plurality of outputs of said shift register, said second input receiving said first logic state of said first control signal, said output providing said first enable signal.

12. The phase lock loop of claim 11 wherein the VCO includes:

a first inverter having an input, an output and a control input, said control input receiving said predetermined voltage from said loop node for frequency controlling said oscillator signal of said VCO;

a second inverter having an input coupled to said output of said first inverter and having an output; and

a third inverter having an input coupled to said output of said second inverter and having an output for providing said oscillator signal of said VCO, said output being coupled to said input of said first inverter.

13. The phase lock loop of claim 12 wherein said load circuit includes a second output coupled to said output of said second inverter and a third output coupled to said output of said first inverter.

14. The phase lock loop of claim 13 further comprising:

a second control circuit responsive to said first logic state from a second one of said plurality of outputs of said shift register and said first logic state of said first control signal for providing a second enable signal; and

a second counter having an enable input and a plurality of outputs coupled to a second control input of said load circuit, said enable input receiving said second enable signal, said plurality of outputs providing a second digital value which increments at each second enable signal to increase loading on said second inverter.

15. The phase lock loop of claim 14 further comprising:

a third control circuit responsive to said first logic state from a third one of said plurality of outputs of said shift register and said first logic state of said first control signal for providing a third enable signal; and

a third counter having an enable input and a plurality of outputs coupled to a third control input of said load circuit, said enable input receiving said third enable signal, said plurality of outputs providing a third digital value which increments at each third enable signal to increase loading on said first inverter.

16. The phase lock loop of claim 15 wherein said second control circuit includes a second AND gate having first and second inputs and an output, said first input being coupled to said second one of said plurality of outputs of said shift register, said second input receiving said first logic state of said first control signal, said output providing said second enable signal.

17. The phase lock loop of claim 16 wherein said third control circuit includes a third AND gate having first and second inputs and an output, said first input being coupled to said third one of said plurality of outputs of said shift register, said second input receiving said first logic state of said first control signal, said output providing said third enable signal.