Array of field effect transistors of different threshold voltages in same semiconductor integrated circuit

• US 5,285,069 A
• Filed: 11/21/1991
• Issued: 02/08/1994
• Est. Priority Date: 11/21/1990
• Status: Expired due to Fees

• Current Assignee: Ricoh Company Limited
• Original Assignee: Ricoh Company Limited
• Inventors: Aota, Hideyuki, Kaibara, Mitsuo, Yamanaka, Seiji, Maruyama, Takako, Okubo, Hiizu
• Primary Examiner(s): Mintel, William
• Assistant Examiner(s): LOKE, STEVEN HO YIN
• Application Number:
  US07/795,834
• Time in Patent Office: 810 Days
• Field of Search: 357/23.1, 357/23.12, 357/23.13, 357/45, 357/47, 357/48, 357/53, 257/203, 257/204, 257/206, 257/208, 257/357, 257/360, 257/369, 257/391, 257/392, 257/393, 257/402, 257/404, 257/903, 257/904, 257/390, 257/544
• US Class Current: 257/392
• CPC Class Codes: H01L 27/11807 CMOS gate arrays
• CPC Class Codes: Y10S 257/903 FET configuration adapted for use as static memory cell

Abstract

A semiconductor integrated circuit apparatus has a basic cell region formed by arranging a plurality of basic cells each including a MOS transistor in longitudinal and transversal directions. The MOS transistor has source-drain section diffusive regions formed on a semiconductor substrate, and a gate electrode formed on a channel region between these source-drain section diffusive regions through a gate insulating film. One portion or all of the channel region of at least one MOS transistor within the basic cell region has an impurity concentration different from that in the channel region of another MOS transistor of the same conductivity type within the same basic cell. For example, a threshold voltage in the channel region of a MOS transistor is increased until about 6 volts by implanting ions into the channel region. No MOS transistor is operated at a power voltage such as 5 volts and separates MOS transistors on both sides thereof from each other. Wiring is formed on the MOS transistor and the gate electrode is used as the wiring, thereby improving wiring efficiency.

Claims

1. A semiconductor integrated circuit apparatus comprising:

a basic cell region formed by arranging a plurality of basic cells, each of said plurality of basic cells including a plurality of MOS transistors, in longitudinal and transversal directions;

each of said plurality of MOS transistors having source and drain section diffusive regions, implanted with impurities of a conductivity type opposite to that in said diffusive regions, formed on a semiconductor substrate, and a gate electrode formed on a channel region between said source and drain section diffusive regions through a gate insulating film;

the semiconductor integrated circuit apparatus being constructed such that the source and drain section diffusive regions of a first one of said plurality of MOS transistors is deeply implanted with said impurities at a high concentration and a withstand voltage of a first PN-junction between the diffusive region and the substrate of the first MOS transistor is lower than that of a second PN-junction between the substrate and a diffusive region of a second MOS transistor.

2. A semiconductor integrated circuit apparatus as claimed in claim 1, wherein said first PN-junction having the lower withstand voltage is used as a surge protecting element in a terminal section.

3. A semiconductor integrated circuit apparatus as claimed in claim 1, wherein said first PN-junction having the lower withstand voltage has Zener characteristics.

4. A static RAM formed on a semiconductor integrated circuit of a master slice type formed by arranging a plurality of basic cells, each of said plurality of basic cells composed of a P-channel type MOS transistor and an N-channel type MOS transistor, on the same semiconductor chip in longitudinal and transversal directions, said static RAM comprising:

a first MOS transistor of a memory cell in which a pair of CMOS inverter circuits are connected to each other;

a second MOS transistor for access which is connected to each of memory nodes and has a word line signal as a gate input,

ions being implanted into a channel of at least one of said first and second MOS transistors to change operating characteristics of the memory cell so that an operating state of the memory cell is set to an initial state when a predetermined voltage is applied to the memory cell from a bit line through the MOS transistor for access.

5. A static RAM as claimed in claim 4, wherein the ions are implanted into one portion of said channel region in said at least one MOS transistor so as to set a threshold voltage in this ionic implanting portion such that no channel is formed at a normal power potential and narrow an effective channel width.

6. A static RAM as claimed in claim 4, wherein the ions are implanted into an entire region of said channel in said at least one MOS transistor having the implanted ions such that a threshold voltage of said at least one MOS transistor is equal to a predetermined value for forming the channel at a normal power potential.

7. A master slice type semiconductor integrated circuit apparatus comprising:

a basic cell region in which a plurality of basic cells are arranged, each of the basic cells including a plurality of MOS transistors, each of said plurality of MOS transistors having source and drain section diffusive regions formed on a semiconductor substrate and a gate electrode formed on a channel between said source and drain section diffusive regions through a gate insulating film;

wherein ions are implanted into a part of the channel of at least one of the plurality of MOS transistors included in a basic cell to change the effective channel width of said at least one of the plurality of MOS transistors in such a manner that a threshold level of voltage of the implanted part is set at a voltage level in which said part of the channel does not operate within a normal operating voltage of a current source.

8. A master slice type semiconductor integrated circuit apparatus according to claim 7, wherein the ions are implanted in such a manner as to change a threshold level of a logic element.

9. A master slice type semiconductor integrated circuit apparatus according to claim 7, wherein the apparatus is constructed in such a manner as to control an ON electric current of said at least one of the plurality of MOS transistors.

10. A master slice type semiconductor integrated circuit apparatus according to claim 7, wherein the apparatus is constructed in such a manner as to control a rising up or a falling down of an output signal of said at least one of the plurality of MOS transistors.

11. A master slice type semiconductor integrated circuit apparatus as set forth in claim 7, wherein the apparatus is constructed as a SRAM in which characteristics of memory cells are changed and a writing is executed by a single signal.

12. A master slice type semiconductor integrated circuit apparatus as set forth in claim 7, wherein the apparatus is constructed as a SRAM in which characteristics of memory cells are changed and an initializing is executed.

13. A master slice type semiconductor integrated circuit apparatus comprising:

a basic cell region in which a plurality of basic cells are arranged, each of the basic cells including a MOS transistor;

said MOS transistor having source and drain diffusive regions formed on a semiconductor substrate;

wherein ions are implanted into all of the channel of at least one of the MOS transistors in such a manner that a threshold level of voltage of said channel is set at a voltage level in which said channel does not operate within a normal operating voltage of a current source so that a gate electrode of said at least one MOS transistor is used as a wiring formed on said channel between said source and drain diffusive regions through a gate insulating film.

14. A master slice type semiconductor integrated circuit apparatus comprising:

a basic cell region in which a plurality of basic cells are arranged, each of the basic cells including a plurality of MOS transistors;

each of said plurality of MOS transistors having source and drain section diffusive regions implanted with impurities of a conductivity type opposite to that in said diffusive regions formed on a semiconductor substrate and a gate electrode formed on a channel through a gate insulating film;

wherein impurities are deeply implanted into the source and drain diffusive regions of a first one of said plurality of MOS transistors at a high density, and a breakdown voltage of a first PN-junction between the diffusive region and the substrate of the first MOS transistor is lower than the breakdown voltage of a second PN-junction between the substrate and the diffusive region of a second MOS transistor into which the impurities are not deeply implanted.

15. A master slice type semiconductor integrated circuit apparatus as claimed in claim 14, wherein said first PN-junction having the lower breakdown voltage is used as a surge protecting element in a terminal section.

16. A master slice type semiconductor integrated circuit apparatus as claimed in claim 14, wherein said first PN-junction having the lower breakdown voltage has Zener characteristics.