Variable resistor and neuro device using the variable resistor for weighting

• US 5,296,835 A
• Filed: 06/30/1993
• Issued: 03/22/1994
• Est. Priority Date: 07/01/1992
• Status: Expired due to Term

• Current Assignee: ROHM Co., Ltd.
• Original Assignee: ROHM Co., Ltd.
• Inventors: Nakamura, Takashi
• Primary Examiner(s): Lateef, Marvin M.
• Application Number:
  US08/083,570
• Time in Patent Office: 265 Days
• Field of Search: 338/13, 338/20, 338/204, 338/322, 338/332, 338/333, 338/334, 257/536, 257/537
• US Class Current: 338/130
• CPC Class Codes: G06N 3/063 using electronic means
• CPC Class Codes: G11C 11/54 using elements simulating biological cells, e.g. neuron
• CPC Class Codes: H01C 7/105 Varistor cores H01C7/12 takes precedence
• CPC Class Codes: H10N 70/063 by etching of pre-deposited switching material layers, e.g. lithography
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/841 Electrodes
• CPC Class Codes: H10N 70/8822 Sulfides, e.g. CuS
• CPC Class Codes: H10N 70/8828 Tellurides, e.g. GeSbTe

Abstract

A Neuro device is a representation of a nerve cell constituting human brains, eyes and the like, that is, a neuron by an electronic circuit. A circuit of the Neuro device according to the present invention comprises n (n : natural number) input terminals 4, n variable resistors 8 (the resistance values of the n variable resistors 8 are respectively set to R1, R2,..., Rn) respectively connected to the input terminals 4, and an arithmetic circuit 100 to which signals from the variable resistors 8 are together applied, and an output terminal 5 to which a signal from the arithmetic circuit 100 is outputted. The variable resistor 8 is so constructed that a chalcogenide semiconductor is interposed between a pair of electrodes. The chalcogenide semiconductor can be reversibly transferred to a high resistive amorphous state and a low resistive crystallized state by applying a predetermined write voltage. In the present invention, a predetermined proportion of the chalcogenide semiconductor interposed between the pair of electrodes is brought into a crystallized state, while the remaining proportion thereof is brought into an amorphous state, thereby to construct a variable resistor having a desirable resistance value.

Claims

1. A Neuro device comprising:

a plurality of input means to which signals are respectively inputted;

weighting means respectively provided in said plurality of input means for respectively adding to the signals inputted to the input means weights which are determined for the input means,

said weighting means comprising a chalcogenide semiconductor, a predetermined proportion of said chalcogenide semiconductor being transferred to a low resistive crystallized state and the remaining proportion thereof being in a high resistive amorphous state; and

operating means to which the signals respectively having the weights added thereto by said weighting means are respectively applied from said input means,

said operating means adding said signals applied from the respective input means and deriving a predetermined output signal when the total amount of the signals exceeds a predetermined reference amount.

2. The Neuro device according to claim 1, wherein said weighting means comprises

a first electrode;

a second electrode opposed to the first electrode, the spacing between the opposed first and second electrodes being the smallest in one end of a space between the opposed first and second electrodes, while being the largest in the other end thereof, and

a chalcogenide semiconductor with which said space between the opposed first and second electrodes is filled.

3. The Neuro device according to claim 2, wherein

a proportion of the chalcogenide semiconductor which corresponds to the weight added is transferred to said low resistive crystallized state sequentially from the narrowest space between the opposed first and second electrodes to the widest space therebetween by previously applying a predetermined write voltage to the space between the opposed first and second electrodes.

4. The Neuro device according to claim 1, wherein said weighting means comprises

a first electrode,

a second electrode opposed to the first electrode, the spacing between the opposed first and second electrodes being the smallest in one end of the space between the opposed first and second electrodes, while being the largest in the other end thereof,

a chalcogenide semiconductor layer disposed in a predetermined proportion of said space between the opposed first and second electrodes, extending in a direction parallel to the first electrode or the second electrode, and having a predetermined thickness which is not more than the smallest spacing between the opposed first and second electrodes, and

a resistor layer with which the remaining proportion of the space between the opposed first and second electrodes is filled.

5. The Neuro device according to claim 4, wherein

a proportion of the chalcogenide semiconductor which corresponds to the weight added is transferred to said low resistive crystallized state sequentially from the narrowest space between the opposed first and second electrodes to the widest space therebetween by previously applying a predetermined write voltage to the space between the opposed first and second electrodes.

6. A variable resistor comprising:

a plurality of pairs of opposed electrodes which differ in spacing;

a chalcogenide semiconductor with which spaces between said pairs of opposed electrodes are filled; and

connecting means for electrically connecting said plurality of pairs of opposed electrodes in parallel.

7. The variable resistor according to claim 6, wherein

the chalcogenide semiconductor with which the spaces between a predetermined number of pairs of opposed electrodes having relatively large spacing out of said plurality of pairs of opposed electrodes are filled is in a high resistive amorphous state, and

the chalcogenide semiconductor with which the spaces between the remaining number of pairs of opposed electrodes having relatively small spacing are filled is in a low resistive crystallized state.

8. The variable resistor according to claim 6, wherein

said plurality of pairs of opposed electrodes and said connecting means comprise a pair of opposed electrodes,

the spacing between said pair of opposed electrodes is the smallest in one end of the space between the opposed electrodes, while being the widest in the other end thereof.

9. The variable resistor according to claim 8, wherein

the chalcogenide semiconductor with which a predetermined proportion of the space between said pair of opposed electrodes whose spacing is relatively large is filled is in a high resistive amorphous state, and

the chalcogenide semiconductor with which the remaining proportion of the space between the pair of opposed electrodes whose spacing is relatively small is filled is in a low resistive crystallized state.

10. The variable resistor according to claim 6, wherein

said chalcogenide semiconductor comprises a compound expressed by the following molecular formula:

space="preserve" listing-type="equation">As.sub.X S.sub.(1-X), where 0<

X<

1.

11. The variable resistor according to claim 6, wherein

said chalcogenide semiconductor comprises a compound in the form expressed by the following equation:

Ge_A Te_B X_C Y_D, where A, B, C and D are natural numbers, and A+B+C+D=100.

12. The variable resistor according to claim 11, wherein

said chalcogenide semiconductor comprises a compound expressed by the following molecular formula:

space="preserve" listing-type="equation">Ge.sub.24 Te.sub.72 Sb.sub.2 S.sub.2.

13. A variable resistor comprising:

a plurality of chalcogenide semiconductor layers which are equal in thickness;

resistors which are respectively connected in series with said chalcogenide semiconductor layers and differ in resistance value; and

connecting means for electrically connecting series connections of said chalcogenide semiconductor layers and the resistors in parallel.

14. The variable resistor according to claim 13, wherein

a predetermined number of chalcogenide semiconductor layer with which the resistors having a relatively high resistance value are connected in series out of the plurality of chalcogenide semiconductor layers are in a high resistive amorphous state, and

the remaining number of chalcogenide semiconductor layers to which the resistors having a relatively low resistance value are connected are in a low resistive crystallized state.

15. The variable resistor according to claim 13, wherein the series connections of said plurality of chalcogenide semiconductor layers and the resistors and the connecting means comprise

a first electrode,

a second electrode opposed to the first electrode, the spacing between the opposed first and second electrodes being the smallest in one end of a space between the opposed first and second electrodes, while being the largest in the other end thereof,

a chalcogenide semiconductor layer disposed in a predetermined proportion of said space between the opposed first and second electrodes, extending in a direction parallel to the first electrode or the second electrode, and having a predetermined thickness which is not more than the smallest spacing between the opposed first and second electrodes, and

a resistor layer with which the remaining proportion of the space between the opposed first and second electrodes is filled.

16. The variable resistor according to claim 15, wherein

a predetermined proportion of the chalcogenide semiconductor layer is transferred to the low resistive crystallized state sequentially from the narrowest space between the opposed first and second electrodes to the widest space therebetween, while the remaining proportion of the chalcogenide semiconductor layer is in the high resistive amorphous state by previously applying a predetermined write voltage to the space between the opposed first and second electrodes.

17. The variable resistor according to claim 13, wherein

said chalcogenide semiconductor layer comprises a compound expressed by the following molecular formula:

space="preserve" listing-type="equation">As.sub.X S.sub.(1-X), where 0<

X<

1.

18. The variable resistor according to claim 13, wherein

said chalcogenide semiconductor layer comprises a compound in the form expressed by the following molecular formula:

Ge_A Te_B X_C Y_D, where A, B, C and D are natural numbers, and A+B+C+D=100.

19. The variable resistor according to claim 18, wherein

said chalcogenide semiconductor layer comprises a compound expressed by the following molecular formula:

space="preserve" listing-type="equation">Ge.sub.24 Te.sub.72 Sb.sub.2 S.sub.2