Semiconductor memory device

• US 5,297,029 A
• Filed: 12/18/1992
• Issued: 03/22/1994
• Est. Priority Date: 12/19/1991
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Kato, Hideo, Nakai, Hiroto, Asano, Masamichi, Tokushige, Kaoru
• Primary Examiner(s): LaRoche, Eugene R.
• Assistant Examiner(s): ZARABIAN, AMIR
• Application Number:
  US07/993,109
• Time in Patent Office: 459 Days
• Field of Search: 365/238.5, 365/189.12, 365/230.09, 365/239, 365/240, 365/230.01
• US Class Current: 365/238.5
• CPC Class Codes: G06F 3/0601 Interfaces specially adapted for storage systems
• CPC Class Codes: G06F 3/0664 at device level, e.g. emulation of a storage device or system
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 7/103 using serially addressed read-write data registers G11C7/1036 takes precedence
• CPC Class Codes: G11C 8/04 using a sequential addressing device, e.g. shift register, counter

Abstract

In reading data, data is transferred to data registers starting from a data read start address to the last address at a row (page), and data at the next page is transferred to the data registers starting from a start address to the last address at that page. These operations are repeated. In writing data from an intermediate address of a page, predetermined data is written in data registers not having write data. It is possible to read data at consecutive pages from a first predetermined column address to the page last address, and to read data at consecutive pages from a second predetermined column address to the page last address. For the data structure having a first data structure and a second data structure, it is possible to continuously read a set of data having both the first and second data structures and a set of data having only the second data structure, improving the efficiency of a system using a semiconductor memory device.

Claims

1. A semiconductor memory device having a plurality of memory cells disposed in a matrix form, data in said memory cells at a selected row being transferred in parallel to a plurality of data registers, the data transferred in said data registers being serially outputted to an external circuit, and the above-described operations being repeated to allow a page data read operation, comprising:

address input means for storing a data read start address inputted from said external circuit;

address control means for incrementing an internal address stored in said address input means;

read means for transferring data in said memory cells to said data registers after outputting data of one page from said data registers; and

busy signal output means for outputting a busy signal indicating a disabled access to said external circuit while said read means is transferring data.

4. A semiconductor memory device according to claim 1, wherein when said read start address inputted from said external circuit is stored in said address input means, said data in said memory cells is automatically transferred to said data registers and said busy signal is automatically outputted to said external circuit.

2. A semiconductor memory device having a plurality of memory cells disposed in a matrix form, and a plurality of data stored from an external circuit in a plurality of data registers being written simultaneously in said memory cells at a selected row to allow a page data write operation, comprising:

address input means for storing a data write start address inputted from said external circuit;

address control means for incrementing an internal address stored in said address input means;

data input means for writing data from said external circuit into said data registers among said plurality of data registers designated by said internal addresses; and

data setting means for setting data in the other data registers not written with data to a predetermined write data.

3. A semiconductor memory device having a plurality of memory cells disposed in a matrix form, data in said memory cells at a selected row being transferred in parallel to a plurality of data registers, the data transferred in said data registers being serially outputted to an external circuit, the above-described operations being repeated, a plurality of data stored from said external circuit in said plurality of data registers being written simultaneously in said memory cells at a selected row, to allow page data read and write operations, comprising:

address input means for storing a data read start address inputted from said external circuit;

address control means for incrementing an internal address stored in said address input means;

read means for transferring data in said memory cells to said data registers after outputting data of one page from said data registers;

busy signal output means for outputting a busy signal indicating a disabled access to said external circuit while said read means is transferring data;

data input means for writing data from said external circuit into said data registers among said plurality of data registers designated by said internal addresses; and

data setting means for setting data in the other data registers not written with data to a predetermined write data.

5. A semiconductor memory device having a plurality of memory cells disposed in a matrix form, a plurality of data registers for temporarily storing data at each column, and a page read mode for storing page data in said memory cells at a selected row in said data registers and sequentially outputting said page data in said data registers to an external circuit, comprising:

a first mode for sequentially outputting, when said selected row is changed, the contents of said data registers to said external circuit starting from a first predetermined column; and

a second mode for sequentially outputting, when said selected row is changed, the contents of said data registers to said external circuit starting from a second predetermined column.

6. A semiconductor memory device having a plurality of memory cells disposed in a matrix form, a plurality of data registers for temporarily storing data at each column, and a page read mode for storing page data in said memory cells at a selected row in said data registers and sequentially outputting said page data in said data registers to an external circuit, comprising:

control means for controlling to sequentially output in a first mode, when said selected row is changed, the contents of said data registers to said external circuit starting from a first predetermined column, and to sequentially output in a second mode, when said selected row is changed, the contents of said data registers to said external circuit starting from a second predetermined column.