Method of fabricating highly lattice mismatched quantum well structures

• US 5,300,794 A
• Filed: 03/19/1991
• Issued: 04/05/1994
• Est. Priority Date: 09/25/1989
• Status: Expired due to Term

• Current Assignee: GTE Laboratories Incorporated (Lumen Technologies, Inc.)
• Original Assignee: GTE Laboratories Incorporated (Lumen Technologies, Inc.)
• Inventors: Melman, Paul, Elman, Boris S., Koteles, Emil S., Jagannath, Chirravuri
• Primary Examiner(s): Crane, Sara W.
• Application Number:
  US07/671,311
• Time in Patent Office: 1,113 Days
• Field of Search: 357/16, 357/45 L, 257/14, 257/15, 257/190
• US Class Current: 257/190
• CPC Class Codes: B82Y 20/00 Nanooptics, e.g. quantum optics or photonic crystals
• CPC Class Codes: H01L 21/02395 Arsenides
• CPC Class Codes: H01L 21/02463 Arsenides
• CPC Class Codes: H01L 21/02507 Alternating layers, e.g. superlattice
• CPC Class Codes: H01L 21/02546 Arsenides
• CPC Class Codes: H01S 5/34 comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers H01S5/36 takes precedence
• CPC Class Codes: H01S 5/3403 having a strained layer structure in which the strain performs a special function, e.g. general strain effects, strain versus polarisation
• CPC Class Codes: H01S 5/3406 including strain compensation
• CPC Class Codes: Y10S 148/06 Gettering
• CPC Class Codes: Y10S 148/097 Lattice strain and defects
• CPC Class Codes: Y10S 148/16 Superlattice
• CPC Class Codes: Y10S 438/936 Graded energy gap
• CPC Class Codes: Y10S 438/938 Lattice strain control or utilization

Abstract

A method of fabricating a semiconductor heterostructure includes the growth of a quantum well active region that is highly lattice-mismatched relative to a substrate. A buffer layer having a thickness above a critical value is grown on the substrate whereby the stress due to a lattice constant mismatch between the buffer layer and substrate is relieved through the formation of misfit dislocations. A strained superlattice structure is grown on the buffer layer in order to terminate any upwardly-propagating dislocations. An unstrained barrier layer is subsequently grown on the superlattice structure. The fabrication method concludes with the growth of a quantum well structure on the unstrained layer wherein a lattice constant mismatch between the quantum well structure and the unstrained barrier layer is smaller than the lattice constant mismatch between the quantum well structure and the substrate. As a result, only a fraction of the stress due to the large lattice mismatch between the quantum well structure and the substrate is accommodated by coherent strain in the quantum well structure, while the remainder of the stress is relieved through the formation of misfit dislocations spatially separated from the quantum well structure.

Claims

1. A semiconductor heterostructure, comprising:

a host substrate;

a buffer layer of uniformly compositioned semiconducting material grown on said substrate wherein said layer is lattice-mismatched relative to said substrate;

a strained superlattice structure grown on said buffer layer wherein said host substrate, said buffer layer, and said superlattice structure together form an effective substrate;

an unstrained barrier layer grown on said superlattice structure; and

a quantum well structure serving as an active region and grown on said barrier layer;

wherein said uniformly compositioned buffer layer has a thickness greater than a critical thickness such that stress due to a lattice constant mismatch between said quantum well structure and said host substrate is accommodated by the formation of dislocations in said uniformly compositioned buffer layer.

2. The semiconductor heterostructure as recited in claim 1 further includes:

an upper barrier layer grown on said quantum well structure; and

a superlattice structure grown on said upper barrier layer.

3. The semiconductor heterostructure as recited in claim 1 wherein the unstrained barrier layer includes:

a semiconductor layer of uniform composition; and

superlattice structure grown on said uniform compositional layer and having a graded composition.

4. The semiconductor heterostructure as recited in claim 1 wherein:

said superlattice structure is strain symmetrized.

5. The semiconductor heterostructure as recited in claim 2 further includes

a cap layer grown on the superlattice structure grown on said upper barrier layer.

6. The semiconductor heterostructure as recited in claim 1 wherein

a lattice constant mismatch between said quantum well structure and said barrier layer is smaller than the lattice constant mismatch between said quantum well structure and said host substrate.