Semiconductor integrated circuit device having single-element type non-volatile memory elements
First Claim
1. A semiconductor integrated circuit device having an electrically erasable programmable read only memory (EEPROM) including a plurality of memory cells each of which is constituted by a single field effect transistor, said memory cell comprising:
- a control gate coupled to a word line;
a floating gate positioned under said control gate;
a first gate insulation film formed between a main surface of a semiconductor substrate and said floating gate;
a second gate insulation film formed between the two gates;
source and drain regions formed in said semiconductor substrate at said main surface and on opposite sides of a channel forming region positioned beneath the two gates, said source and drain regions being of a first conductivity type and said channel forming region being of a second conductivity type, said source region having a doping concentration which is higher than that of said drain region and which prevents surface depletion when high voltage is applied to said source region during an erasing operation of said memory, the junction depth of said source region into said semiconductor substrate, with respect to said main surface thereof, being greater than that of said drain region, and said first gate insulation film having a predetermined film thickness so as to permit tunneling of electrons from said floating gate, during the erasing operation of said memory, to said semiconductor substrate through said first gate insulation film; and
a semiconductor region of said second conductivity type formed in said semiconductor substrate and having a doping concentration higher than that of said channel forming region, said semiconductor region being brought into contact with said drain region at the channel forming region side thereof,wherein said drain region operates as the drain of said single field effect transistor in both write and read modes of said EEPROM,wherein said memory cell stores data when a first predetermined potential is applied to said drain region, andwherein the data of said memory cell is read when a second predetermined potential is applied to said drain region, said second predetermined potential is lower in magnitude than said first predetermined potential.
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Accused Products
Abstract
A semiconductor integrated device having a non-volatile memory element or memory cell of a single-element type in a non-volatile memory circuit employing a field effect transistor which has, in addition to a floating gate electrode for storage of information and a controlling gate electrode, a source which includes a heavily doped region having a depth into the semiconductor substrate extending from the major surface thereof which is large. The single-element type field effect transistor, furthermore, has a drain which includes a lightly doped region which has a depth extending into the semiconductor substrate from the major surface thereof which is small.
48 Citations
34 Claims
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1. A semiconductor integrated circuit device having an electrically erasable programmable read only memory (EEPROM) including a plurality of memory cells each of which is constituted by a single field effect transistor, said memory cell comprising:
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a control gate coupled to a word line; a floating gate positioned under said control gate; a first gate insulation film formed between a main surface of a semiconductor substrate and said floating gate; a second gate insulation film formed between the two gates; source and drain regions formed in said semiconductor substrate at said main surface and on opposite sides of a channel forming region positioned beneath the two gates, said source and drain regions being of a first conductivity type and said channel forming region being of a second conductivity type, said source region having a doping concentration which is higher than that of said drain region and which prevents surface depletion when high voltage is applied to said source region during an erasing operation of said memory, the junction depth of said source region into said semiconductor substrate, with respect to said main surface thereof, being greater than that of said drain region, and said first gate insulation film having a predetermined film thickness so as to permit tunneling of electrons from said floating gate, during the erasing operation of said memory, to said semiconductor substrate through said first gate insulation film; and a semiconductor region of said second conductivity type formed in said semiconductor substrate and having a doping concentration higher than that of said channel forming region, said semiconductor region being brought into contact with said drain region at the channel forming region side thereof, wherein said drain region operates as the drain of said single field effect transistor in both write and read modes of said EEPROM, wherein said memory cell stores data when a first predetermined potential is applied to said drain region, and wherein the data of said memory cell is read when a second predetermined potential is applied to said drain region, said second predetermined potential is lower in magnitude than said first predetermined potential. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A semiconductor integrated circuit device having an electrically erasable programmable read only memory which includes a memory cell constituted by a single field effect transistor, said memory cell comprising:
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a controlling gate coupled to a word line; a floating gate positioned under said control gate; a first gate insulation film formed between a main surface of a semiconductor substrate and said floating gate; a second gate insulation film formed between the two gates; source and drain regions formed in said semiconductor substrate at said main surface and on opposite sides of a channel forming region positioned beneath the two gates, said source and drain regions being of a first conductivity type and said semiconductor substrate being of a second conductivity type, said source region having a doping concentration higher than that of said drain region so as to prevent surface depletion when high voltage is applied to said source region at the time of an information erasing operation and said source region having a junction depth into said semiconductor substrate, with respect to said main surface thereof, greater than said drain region; and a semiconductor region of said second conductivity type formed in said semiconductor substrate and having a doping concentration higher than that of said channel forming region, said semiconductor region being brought into contact with said drain region so as to enhance the intensity of an electric field in the vicinity of said drain region during an information writing operation of said memory cell, wherein said drain region operates as the drain of said single field effect transistor in both write and read mode of said EEPROM, wherein said memory cell stores data when a first predetermined potential is applied to said drain region, and wherein the data of said memory cell is read when a second predetermined potential is applied to said drain region, said second predetermined potential is lower in magnitude than said first predetermined potential. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29)
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30. A semiconductor integrated circuit device having an electrically erasable programmable read only memory (EEPROM) including a memory cell which is constituted by a single field effect transistor, said memory cell comprising:
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a control gate; a floating gate positioned under said control gate; a first gate insulation film formed between a main surface of a semiconductor substrate and said floating gate; a second gate insulation film formed between the two gates; and source and drain regions formed in said semiconductor substrate at said main surface and on opposite sides of a channel forming region positioned beneath the two gates, said source and drain regions being of a first conductivity type, said channel forming region being a second conductivity type, said source region including a first region extending under said floating gate, said drain region including a second region being formed as a substrate surface region adjacent said channel forming region and having a doping concentration lower than that of said first region, and the junction depth of said first region into said semiconductor substrate, with respect to said main surface thereof, being greater than that of said second region, wherein said source region further includes a third region surrounding said first region, said third region has a doping concentration lower than that of said first region, wherein said memory cell stores data, when a first predetermined potential is applied to said drain region, by injecting hot carriers, which are generated in said semiconductor substrate in the vicinity of said second region, into said floating gate, wherein said memory cell erases the data, when a second predetermined potential is applied between said source region and said control gate, by emitting said injected carriers from said floating gate to said first region by tunneling through said first gate insulation film, and wherein the data of said memory cell is read when a third predetermined potential is applied to said drain region, said third potential is lower in magnitude than said first predetermined potential and said first, second and third predetermined potentials have the same polarity.
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31. A semiconductor integrated circuit device having an electrically erasable programmable read only memory (EEPROM) including a memory cell which is constituted by a single field effect transistor, said memory cell comprising:
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a control gate; a floating gate positioned under said control gate; a first gate insulation film formed between a main surface of a semiconductor substrate and said floating gate; a second gate insulation film formed between the two gates; source and drain regions formed in said semiconductor substrate at said main surface and on opposite sides of a channel forming region positioned beneath the two gates, said source and drain regions being of a first conductivity type, said channel forming region being a second conductivity type, said source region including a first region extending under said floating gate, said drain region including a second region being formed as a substrate surface region adjacent said channel forming region and having a doping concentration lower than that of said first region, and the junction depth of said first region into said semiconductor substrate, with respect to said main surface thereof, being greater than that of said second region; and a semiconductor region of said second conductivity type formed in said semiconductor substrate, said semiconductor region being in contact with said second region on the channel region side thereof, and said semiconductor region having a doping concentration higher than that of said channel forming region, wherein said memory cell stores data, when a first predetermined potential is applied to said drain region, by injecting hot carriers, which are generated in said semiconductor substrate in the vicinity of said second region, into said floating gate, wherein said memory cell erases the data, when a second predetermined potential is applied between the source region and said control gate, by emitting said injected carriers from said floating gate to said first region by tunneling through said first gate insulation film, and wherein the data of said memory cell is read when a third predetermined potential is applied to said drain region, said third potential is lower in magnitude than said first predetermined potential and said first, second and third predetermined potentials have the same polarity. - View Dependent Claims (32)
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33. An electrically erasable memory device including a plurality of memory cells each of which is constituted by a single field effect transistor, said memory cell comprising:
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a control gate coupled to a word line; a floating gate positioned under said control gate; a first gate insulation film formed between a main surface of a semiconductor substrate and said floating gate; a second gate insulation film formed between the two gates; source and drain regions formed in said semiconductor substrate at said main surface and on opposite sides of a channel forming region positioned beneath the two gates, said source and drain regions being of n-type conductivity, said channel forming region being p-type conductivity, said source region including a first region extending under said floating gate, said drain region including a second region being formed as a substrate surface region adjacent said channel forming region, the junction depth of said first region into said semiconductor substrate, with respect to said main surface thereof, being greater than that of said second region; and a semiconductor region of p-type conductivity type formed in said semiconductor substrate, said semiconductor region is in contact with said second region on the channel region side thereof, wherein said memory cell stores data, when a first predetermined potential is applied to said drain region, by injecting hot electrons, which are generated in said semiconductor substrate in the vicinity of said second region, into said floating gate during a writing operation, wherein said memory cell erases the data, when a second predetermined potential is applied between said first region and said control gate, by emitting said injected electrons from said floating gate to said first region by tunnelling through said first gate insulation film during an erasing operation; wherein said first region has a doping concentration higher than that of said second region so as to reduce surface depletion of said first region at the time of said erasing operation, wherein said semiconductor region has a doping concentration higher than that of said channel forming region so as to enhance the intensity of an electric field in the vicinity of said second region for increasing the generation of hot electrons at the time of said writing operation, and wherein the data of said memory cell is read when a third predetermined potential is applied to said drain region, said third predetermined potential is lower in magnitude than said first predetermined potential. - View Dependent Claims (34)
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Specification