Network adapter with host indication optimization
DC CAFCFirst Claim
1. An apparatus for transferring a data frame between a network transceiver, coupled with a network, and a host system which includes a host processor and host memory, the apparatus generating an indication signal to the host processor responsive to the transfer of the data frame, with the host processor responding to the indication signal after a period of time, comprising:
- a buffer memory for storing the data frame;
network interface logic for transferring the data frame between the network transceiver and the buffer memory;
host interface logic for transferring the data frame between the host system and the buffer memory;
threshold logic for allowing the period of time for the host processor to respond to the indication signal to occur during the transferring of the data frame, wherein the threshold logic includes,a counter, coupled to the buffer memory, for counting the amount of data transferred to or from the buffer memory;
an alterable storage location containing a threshold value; and
means for comparing the counter to the threshold value in the alterable storage location and generating an indication signal to the host processor responsive to a comparison of the counter and the alterable storage location.
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Abstract
Optimized indication signals of a completed data frame transfer are generated by a network adapter which reduces host processor interrupt latency. The network adapter comprises network interface logic for transferring the data frame between the network and a buffer memory and host interface logic for transferring the data frame between the buffer memory and the host system. The network adapter further includes threshold logic where a threshold value in an alterable storage location is compared to a data transfer counter in order to generate an early indication signal. The early indication signal may be used to generate an early interrupt signal to a host processor before a transfer of a data frame is completed. The network adapter also posts status information status registers which may be used by the host processor to tune the timing of the generation of the network adapter interrupt signal.
94 Citations
53 Claims
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1. An apparatus for transferring a data frame between a network transceiver, coupled with a network, and a host system which includes a host processor and host memory, the apparatus generating an indication signal to the host processor responsive to the transfer of the data frame, with the host processor responding to the indication signal after a period of time, comprising:
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a buffer memory for storing the data frame; network interface logic for transferring the data frame between the network transceiver and the buffer memory; host interface logic for transferring the data frame between the host system and the buffer memory; threshold logic for allowing the period of time for the host processor to respond to the indication signal to occur during the transferring of the data frame, wherein the threshold logic includes, a counter, coupled to the buffer memory, for counting the amount of data transferred to or from the buffer memory; an alterable storage location containing a threshold value; and means for comparing the counter to the threshold value in the alterable storage location and generating an indication signal to the host processor responsive to a comparison of the counter and the alterable storage location. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21)
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22. A network adapter for receiving a data frame from a network transceiver, coupled with a network and a host system which includes an interruptable host processor with interrupt latency and host memory, comprising:
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a buffer memory for storing the data frame; receive logic for receiving the data frame from the network transceiver to the buffer memory; receive threshold logic for generating an indication signal during the receiving of the data frame, wherein the receive threshold logic includes, a counter, coupled to the buffer memory, for counting the amount of data received by the buffer memory; an alterable storage location containing a receive threshold value; means for comparing the counter to the receive threshold value in the alterable storage location and generating an indication signal responsive to a comparison of the counter and the alterable storage location; and host interface logic for transferring the data frame from the buffer memory to the host system, wherein host interface logic includes, control means for generating an interrupt signal to the host processor, responsive to the indication signal, which reduces host processor interrupt latency. - View Dependent Claims (23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33)
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34. A network adapter for receiving a data frame which includes a header field followed by a data field from a network transceiver, coupled with a network and a host system which includes an interruptable host processor with interrupt latency and host memory, comprising:
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a buffer memory for storing the data frame; receive logic for receiving the data frame from the network transceiver to the buffer memory; look-ahead threshold logic for generating an early receive indication signal during the receiving of the data frame, wherein the receive threshold logic includes, a counter, coupled to the buffer memory, for counting the amount of data received by the buffer memory; an alterable storage location containing a look-ahead threshold value representing an amount of data relative to the beginning of the header field; means for comparing the counter to the look-ahead threshold value in the alterable storage location and generating an early receive indication signal responsive to a comparison of the counter and the alterable storage location; and host interface logic for transferring the data frame from the buffer memory to the host system, wherein host interface logic includes, control means for generating an interrupt signal to the host processor, responsive to the early receive indication signal, which reduces host processor interrupt latency. - View Dependent Claims (35, 36, 37, 38, 39)
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40. A network adapter for receiving a data frame which includes a header field followed by a data field from a network transceiver, coupled with a network and a host system which includes an interruptable host processor with interrupt latency and host memory, comprising:
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a buffer memory for storing the data frame; receive logic for receiving the data frame from the network transceiver to the buffer memory; length-left threshold logic for generating a receive complete indication signal during the receiving of the data frame, wherein the receive threshold logic includes, a counter, coupled to the buffer memory, for counting the amount of data received by the buffer memory; an alterable storage location containing a length-left threshold value representing an amount of data relative to the end of the data field; means for comparing the counter to the length-left threshold value in the alterable storage location and generating a receive complete indication signal responsive to a comparison of the counter and the alterable storage location; and host interface logic for transferring the data frame from the buffer memory to the host system, wherein host interface logic includes, control means for generating an interrupt signal to the host processor, responsive to the receive complete indication signal, which reduces host processor interrupt latency. - View Dependent Claims (41, 42, 43)
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44. A network adapter for transferring a data frame from a network transceiver, coupled with a network and a host system which includes an interruptable host processor with interrupt latency and host memory, comprising:
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a buffer memory for storing the data frame, which includes a data field; receive logic for receiving the data frame from the network transceiver to the buffer memory; transfer threshold logic for generating an early transfer indication signal during the transferring of the data frame from the buffer memory to the host system, wherein the transfer threshold logic includes, a counter, coupled to the buffer memory, for counting the amount of data transferred from the buffer memory; an alterable storage location containing a transfer threshold value; means for comparing the counter to the transfer threshold value in the alterable storage location and generating an early transfer indication signal responsive to a comparison of the counter and the alterable storage location; and host interface logic for transferring the data frame from the buffer memory to the host system, wherein host interface logic includes, control means for generating an interrupt signal to the host processor, responsive to the early transfer indication signal, which reduces host processor interrupt latency. - View Dependent Claims (45, 46, 47, 48, 49)
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50. A network adapter for transmitting a data frame across a communication medium, the network adapter coupled to the communicating medium and a host system which includes an interruptable host processor with interrupt latency and host memory, comprising:
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a buffer memory for storing the data frame; communication interface logic for transmitting the data frame across the communication media from the buffer memory; transmit threshold logic for generating an early transmit indication signal during the transmitting of the data frame, wherein the transmit threshold logic includes, a counter, coupled to the buffer memory, for counting the amount of data transmitted from the buffer memory; an alterable storage location containing a transmit threshold value, representing the amount of data to be transmitted across the communication media; means for comparing the counter to the transmit threshold value in the alterable storage location and generating a transmit complete indication signal responsive to a comparison of the counter and the alterable storage location; and host interface logic for transferring the data frame from the host system to the buffer memory, wherein host interface logic includes, control means for generating an interrupt signal to the host processor, responsive to the early transmit indication signal, which reduces host processor interrupt latency. - View Dependent Claims (51)
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52. A network adapter for transmitting a data frame across a communication medium, the network adapter coupled to the communication medium and a host system which includes an interruptable host processor with interrupt latency and host memory, comprising:
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a buffer memory for storing the data frame; communication interface logic for transmitting the data frame across the communication medium from the buffer memory; download transmit threshold logic for generating an early download transmit indication signal during the transferring of the data frame from the host system to the buffer memory, wherein the receive threshold logic includes, a counter, coupled to the buffer memory, for counting the amount of data transferred to the buffer memory; an alterable storage location containing a download transmit threshold value representing the amount of data transferred to the buffer memory for transmitting across the communication media; means for comparing the counter to the download transmit threshold value in the alterable storage location and generating an indication signal responsive to a comparison of the counter and the alterable storage location; and host interface logic for transferring the data frame from the host system to the buffer memory, wherein host interface logic includes, control means for generating an interrupt signal to the host processor, responsive to the early download transmit indication signal, which reduces host processor interrupt latency. - View Dependent Claims (53)
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Specification