R.F. switching circuits

• US 5,313,083 A
• Filed: 06/28/1993
• Issued: 05/17/1994
• Est. Priority Date: 12/16/1988
• Status: Expired due to Term

• Current Assignee: Raytheon Company (Rtx Corporation)
• Original Assignee: Raytheon Company (Rtx Corporation)
• Inventors: Schindler, Manfred J.
• Primary Examiner(s): Larkins, William D.
• Assistant Examiner(s): Meier, Stephen D.
• Application Number:
  US08/084,790
• Time in Patent Office: 323 Days
• Field of Search: 357/22 I, 357/22 H, 357/15, 357/23.14, 357/4, 357/23.4, 357/24, 257/280, 257/281, 257/401, 257/472
• US Class Current: 257/280
• CPC Class Codes: H01L 29/41758 for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular H01L29/41733 - H01L29/4175 take precedence
• CPC Class Codes: H01L 29/42316 for field-effect transistors
• CPC Class Codes: H01L 29/812 with a Schottky gate H01L29/7725, H01L29/775, H01L29/778, H01L29/806 take precedence; with Schottky contact on top of heterojunction gate H01L29/802
• CPC Class Codes: H03K 17/693 Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors logic circuits H03K19/00; code converters H03M5/00, H03M7/00

Abstract

An advanced MESFET switching structure which includes an interdigitated source region and an interdigitated drain region, also includes a gate electrode region disposed between adjacent portions of the interdigitated source and drain regions having a series gate electrode in Schottky barrier contact therewith. The use of the series connect gate electrode rather than conventional parallel coupled gate fingers eliminates the need for an airbridge overlays to interconnect the source regions as in a conventional MESFET transducer. Moreover, the topography permits smaller MESFET structures and thus higher integration of circuits employing the advanced MESFET switch structure. The smaller transistors will also have lower parasitic reactances. In a preferred embodiment, all interconnections for drain, gate, and source electrodes are disposed on the active layer portion of the transistor providing an even smaller transistor structure.

Claims

1. An r.f. switch having a common terminal and at least a pair of branch terminals comprising:

a plurality of metal semiconductor field effect transistors, each transistor having source, drain, and gate electrodes arranged to provide a low impedance path between said common terminal and a first one of said branch terminals and a high impedance path between said common terminal and a second one of said branch terminals in response to a first state of a control signal fed to the gate electrode of said transistors, and a low impedance path between said second branch terminal and said common terminal and a high impedance path between said common terminal and said first branch terminal in response to a second, different state control signal fed to the gate electrodes of said transistors, each of said metal semiconductor field effect transistors comprising;

an active region, comprising doped gallium arsenide supported by said substrate;

a plurality of drain electrode portions disposed in ohmic contact over said active region and spaced along said active region;

a second plurality of source electrode portions disposed in ohmic contact over said active region and spaced along said active region from said electrode portions to provide gate regions of said active layer;

a third plurality of gate electrodes extending along a first direction and disposed in Schottky barrier contact with said active region, with each one of said third plurality of gate electrodes having first and second ends and each of said electrodes being disposed on one of said gate regions of said active region; and

a plurality of interconnect sections extending along a direction perpendicular to the first direction and disposed between the source and drain electrodes in Schottky barrier contact with said active region, to interconnect said third plurality of gate electrodes in a series circuit, with a first one of said pluraliyt of interconnect sections, connected between respective first ends of an adjacent pair of said third plurality of gate electrodes, and with a second one of said plurality of interconnect sections connected to a second end of one of said pair of adjacent gate electrodes and to a corresponding second end of a succeeding one of said plurality of gate electrodes disposed adjacent said one of said pair of adjacent gate electrodes, said gate electrodes and interconnecting sections controlling the flow of carriers between the source and drain electrodes in both the first direction and in the direction perpendicular to the first direction.

2. The transistor as recited in claim 1 wherein the plurality of drain electrode portions are connected to a common drain electrode and wherein the plurality of source electrode portions are connected to a common source electrode.