Alternative body contact for fully-depleted silicon-on-insulator transistors

• US 5,317,181 A
• Filed: 09/10/1992
• Issued: 05/31/1994
• Est. Priority Date: 09/10/1992
• Status: Expired due to Fees

• Current Assignee: UTMC Microelectronic Systems, Inc. (Cobham PLC)
• Original Assignee: United Technologies Corporation (Raytheon Technologies Corporation d/b/a RTX)
• Inventors: Tyson, Scott M.
• Primary Examiner(s): LIMANEK, ROBERT P
• Application Number:
  US07/942,996
• Time in Patent Office: 628 Days
• Field of Search: 257/347, 257/348, 257/349, 257/354, 257/622
• US Class Current: 257/347
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H01L 29/78612 for preventing the kink- or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect

Abstract

Two preferred embodiments for an alternative body contact are disclosed for fully-depleted silicon-on-insulator transistors. In one preferred embodiment, body contact is made by extending the mesa ends of the body ties down to, and merging them with, mesa regions of an nFET source and using self-aligned silicide (commonly known as salicide) to make a connection to an underlying nFET well. In this first embodiment, the mesas of the body ties merge with the mesa of the source and salicide is used to short out these regions. In another preferred embodiment, body contact is made by extending the mesa ends of the body ties down to the nFET source; however, the mesas are not merged. In this second embodiment, metal routing, which is commonly used to electrically connect circuit elements, is extended to connect to the mesa regions of the body ties. In both embodiments, the body ties are active until the onset of full depletion; however, at the onset of full depletion, the body ties are electrically severed.

Claims

1. A transistor formed on an island of silicon over an insulator film over a silicon substrate comprising:

a. a channel region in the silicon island;

b. a source region comprising a mesa formed in the silicon island;

c. a drain region formed in the silicon island and being spaced from the source region and defining the channel region therebetween;

d. a gate extending over the channel region for controlling surface potential in the channel region;

e. an insulator region lying between the gate and the channel and separating the gate from the channel region;

f. at least one body tie region disposed adjacent to and in abutting relation with the channel region and disposed along a predetermined length of the source and being separated from the source by an aperture; and

g. a layer of metal routing overlying the body tie region and the mesa of the source region for electrically connecting the two regions, wherein electrical connection between the channel region and the body tie region is severed when the channel region achieves full depletion.

2. The transistor of claim 1, wherein the transistor is sufficiently doped to create a P channel device.

3. The transistor of claim 1, wherein the transistor is sufficiently doped to create an N channel device.

4. The transistor of claim 1, wherein a plurality of body tie regions extend outwardly from the gate and extend to the mesa of the source region.

5. The transistor of claim 1, wherein the insulator film comprises silicon dioxide.

6. The transistor of claim 1, wherein the insulator film comprises sapphire.

7. The transistor of claim 1, wherein the insulator film comprises spinel.

8. A transistor formed on an island of silicon over an insulator film over a silicon substrate comprising:

a. a channel region in the silicon island;

b. a source region comprising a mesa formed in the silicon island;

c. a drain region formed in the silicon island and being spaced from the source region and defining the channel region therebetween;

d. a gate extending over the channel region for controlling surface potential in the channel region;

e. an insulator region lying between the gate and the channel and separating the gate from the channel region;

f. at least one body tie region disposed adjacent to and in abutting relation with the channel region and disposed along a predetermined length of the source and being separated from the source by an aperture; and

g. a means for electrically connecting the source to the body tie, wherein electrical connection between the channel region and the body tie region is severed when the channel region achieves full depletion.

9. The transistor device of claim 8, wherein the means for electrically connecting the two regions comprises a layer of metal routing overlying the body tie region and the mesa of the source region sufficiently so as to make electrical connection.

10. The transistor of claim 8, wherein the transistor is sufficiently doped to create an P channel device.

11. The transistor of claim 8, wherein the transistor is sufficiently doped to create an N channel device.

12. The transistor of claim 8, wherein a plurality of body tie regions extend outwardly from the gate and extend to the mesa of the source region.

13. The transistor of claim 8, wherein the insulator film comprises silicon dioxide.

14. The transistor of claim 8, wherein the insulator film comprises sapphire.

15. The transistor of claim 8, wherein the insulator film comprises spinel.