Phase locked loop synchronization system for use in data communications
First Claim
1. Apparatus for generating a clock signal which is locked in phase to a received signal having intermittent transitions which are synchronous with a transmitting clock signal having a nominal frequency, said apparatus comprising:
- a source of reference signal having a predetermined frequency which is approximately equal to the nominal frequency;
first variable frequency oscillator means responsive to a coarse control signal for producing an oscillatory output signal;
coarse control means coupled to said first variable frequency oscillator means and responsive to said reference signal and to said oscillatory output signal, for generating said coarse control signal to lock the frequency of said oscillatory output signal to the reference signal;
second variable frequency oscillator means, responsive to a frequency control signal for producing said clock signal; and
fine control means, coupled to said coarse control means and to said second variable frequency oscillator means and responsive to said received signal, for augmenting said coarse control signal to generate said frequency control signal to lock the frequency and phase of said clock signal to said received signal.
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Accused Products
Abstract
A clock generator uses coarse and fine phase locking to lock an internal clock signal to an intermittently received data signal. The clock generator uses separate coarse and fine phase locked loops (PLL'"'"'s). The respective voltage controlled oscillators (VCO'"'"'s) of the PLL'"'"'s are made from matched components and the coarse control signal is applied to both VCO'"'"'s. The fine PLL locks the output signal provided by the second PLL in phase to the received data signal. The oscillatory signal provided by the second PLL is the output clock signal of the system. The fine phase control signal is combined with the coarse frequency control signal to generate the control signal for the second VCO. The fine phase control signal is generated by comparing transitions in a non-return to zero (NRZ) encoded data signal to corresponding transitions in the output clock signal. Phase correction errors made due to missing transitions in the encoded data signal are compensated by one type of phase detector which retains the previous levels of the received data signals. Another type of phase detector gates the clock signal into the loop filter only when it is coincident with detected transitions in the received data signal.
54 Citations
10 Claims
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1. Apparatus for generating a clock signal which is locked in phase to a received signal having intermittent transitions which are synchronous with a transmitting clock signal having a nominal frequency, said apparatus comprising:
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a source of reference signal having a predetermined frequency which is approximately equal to the nominal frequency; first variable frequency oscillator means responsive to a coarse control signal for producing an oscillatory output signal; coarse control means coupled to said first variable frequency oscillator means and responsive to said reference signal and to said oscillatory output signal, for generating said coarse control signal to lock the frequency of said oscillatory output signal to the reference signal; second variable frequency oscillator means, responsive to a frequency control signal for producing said clock signal; and fine control means, coupled to said coarse control means and to said second variable frequency oscillator means and responsive to said received signal, for augmenting said coarse control signal to generate said frequency control signal to lock the frequency and phase of said clock signal to said received signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. Apparatus for generating a clock signal which is locked in phase to a received data signal having intermittent transitions, comprising:
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variable frequency oscillator means, responsive to a control signal, for producing said clock signal; phase detector means including; means responsive to said clock signal and to said received data signal for generating pulses of a first polarity and pulses of a second polarity, opposite to the first polarity, when transitions of said clock signal respectively lead and lag transitions of said received data signal in phase; means for recognizing when a transition in said received data signal did not occur during a previous period of said clock signal and when a pulse of said first polarity was erroneously emitted; and means, coupled to the means for recognizing, for generating a compensating pulse of said second polarity to compensate for the pulse of said first polarity which was erroneously emitted during said previous period of said clock signal; and filter means for combining the pulses of the first and second polarity and the compensating pulses generated by said phase detector means to generate said control signal for said variable frequency oscillator means.
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10. In a data communications system including first and second data processing systems each including a respective internal clock signal generator which provides a respective internal clock signal, and means, coupled to said clock signal generator for encoding data for transmission to the other one of said first and second data processing systems as a data signal, each of said first and second data processing systems further including apparatus for receiving the data signal transmitted by the other one of said first and second data processing systems said apparatus comprising:
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first phase locked loop means responsive to said internal clock signal including means for generating a first control signal and first variable frequency oscillator means, responsive to the first control signal for generating a first output oscillatory signal which is locked in frequency to said internal clock signal; and second phase locked loop means including; second variable frequency oscillator means responsive to a second control signal for generating a second output oscillatory signal which is locked in frequency and phase to said received data signal; phase control means, responsive to said second output oscillatory signal and to said received data signal for generating a phase between said second output oscillatory signal and said received data signal; and means for adding said first control signal and said phase error signal to generate said second control signal for said second variable frequency oscillator means.
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Specification