Two-dimensional array ultrasonic transducers

• US 5,329,496 A
• Filed: 10/16/1992
• Issued: 07/12/1994
• Est. Priority Date: 10/16/1992
• Status: Expired due to Term

• Current Assignee: Duke University, Hjordis Blanchard
• Original Assignee: Duke University
• Inventors: Smith, Stephen W.
• Primary Examiner(s): ELDRED, JOHN W
• Application Number:
  US07/962,455
• Time in Patent Office: 634 Days
• Field of Search: 367/140, 367/153, 367/155, 310/334, 310/336, 310/364, 128/661.01, 128/662.03, 128/663.01, 128/660.01
• US Class Current: 367/140
• CPC Class Codes: B06B 1/064 with multiple active layers
• CPC Class Codes: H04R 17/00 Piezoelectric transducers; Electrostrictive transducers piezoelectric or electrostrictive elements in general H10N30/00; details of piezoelectric or electrostrictive motors, generators or positioners H10N30/00
• CPC Class Codes: H10N 30/092 Forming composite materials
• CPC Class Codes: H10N 30/50 having a stacked or multilayer structure
• CPC Class Codes: H10N 30/872 Connection electrodes of multilayer piezoelectric or electrostrictive devices, e.g. external electrodes
• CPC Class Codes: H10N 30/874 embedded within piezoelectric or electrostrictive material, e.g. via connections

Abstract

A piezoelectric transducer chip comprising a plurality of transducer elements arranged in a two-dimensional array is disclosed. At least one of the transducer elements is a multi-layer element which comprises a plurality of piezoelectric layers, each of which is separated from the adjacent piezoelectric layers by an electrode layer so that a plurality of capacitive elements is electrically connected in parallel. A first via connects a first set of alternating electrode layers, and a second via connects a second set of alternating electrode layers. The first via is insulated from the second set of alternating electrode layers, and the second via is insulated from the first set of alternating electrode layers. At least one of the plurality of multi-layer elements has an internal edge. At least one of the vias of a multi-layer element is an internal via. Also disclosed are an ultrasonic transducer which includes such a piezoelectric chip, and an ultrasonic scanner which includes such a transducer.

Claims

1. A piezoelectric transducer chip comprising:

a plurality of transducer elements a width of from about 0.05 mm to about 1 mm arranged in a two-dimensional array, at least one of said transducer elements being a multilayer element having an internal edge portion and comprising a plurality of piezoelectric layers and a plurality of electrode layers forming a plurality of capacitive elements electrically connected in parallel, each of said plurality of piezoelectric layers being separated from the adjacent piezoelectric layers by one of said plurality of electrode layers, and said piezoelectric layers consisting of a first set of alternating electrode layers and a second set of alternating electrode layers interposed between said first set of alternating electrode layers;

a first via electrically connecting said first set of alternating electrode layers, said first via being electrically insulated from said second set of alternating electrode layers; and

a second via electrically connecting said second set of alternating electrode layers, said second via being electrically insulated from said first set of alternating electrode layers;

wherein at least one of said vias is an internal via.

2. A piezoelectric transducer chip according to claim 1, wherein said plurality of transducer elements comprises a plurality of multilayer elements.

3. A piezoelectric transducer chip according to claim 1, wherein said multilayer element comprises piezoelectric layers which are between about 0.01 and 0.6 mm in thickness.

4. A piezoelectric transducer chip according to claim 1, wherein said multilayer element is substantially square in cross-section.

5. A piezoelectric transducer chip according to claim 1 wherein said first set of alternating electrode layers and said second set of alternating electrode layers each comprise a plurality of electrode layers.

6. A piezoelectric transducer chip according to claim 1, wherein said first via is insulated from said second set of alternating electrodes by a plurality of insulating gaps.

7. A piezoelectric transducer chip according to claim 1, wherein said second via is insulated from said first set of alternating electrodes by a plurality of insulating gaps.

8. A piezoelectric transducer chip according to claim 1, wherein said multiple layer elements are rectangular in cross-section.

9. A piezoelectric transducer chip according to claim 1, wherein at least one of said transducer elements has a single piezoelectric layer.

10. An ultrasonic transducer array comprising:

(a) a connector having an upper surface, a lower surface, and an array of connector pads formed in said connector for electrically connecting said upper surface to said lower surface;

(b) a piezoelectric transducer chip having a plurality of ultrasonic transducer elements arranged in a two-dimensional array, at least one of said ultrasonic transducer elements being a multilayer element having an internal edge portion and comprising a plurality of piezoelectric layers and a plurality of electrode layers forming a plurality of capacitative elements electrically connected in parallel, each of said plurality of piezoelectric layers being separated from the adjacent piezoelectric layers by one of said plurality of electrode layers, and said piezoelectric layers consisting of a first set of alternating electrode layers and a second set of alternating electrode layers interposed between said first set of alternating electrode layers;

(c) a first via connecting said first set of alternating electrode layers, said first via being electrically insulated from said second set of alternating electrode layers; and

(d) a second via connecting in parallel said second set of alternating electrode layers, said second via being electrically insulated from said first set of alternating electrode layers;

wherein at least one of said vias is an internal via;

(e) means for electrically connecting said first set of alternating electrodes to ground; and

(f) means for electrically connecting said second set of alternating electrodes to a corresponding one of said connector pads.

11. An ultrasonic transducer array according to claim 10, which further comprises a metallic ground sheet which overlies said piezoelectric transducer chip and is electrically connected to said means for electrically connecting said first set of alternating electrodes.

12. An ultrasonic transducer array according to claim 10, wherein said means for electrically connecting said second set of alternating electrodes comprises a bonding layer to connect to said upper surface of said connector.

13. An ultrasonic transducer array according to claim 10, wherein said piezoelectric chip comprises a plurality of multilayer elements.

14. An ultrasonic transducer array according to claim 10, wherein said piezoelectric chip comprises at least one multilayer element which includes a first internal edge and a second internal edge, and wherein said first via is an internal via, and wherein said second via is an internal via.

15. Tn ultrasonic transducer array according to claim 10, wherein said ultrasonic transducer operates at a frequency of between about 1 and 10 MHz.

16. An ultrasonic scanner comprising:

(a) means for producing an ultrasonic signal;

(b) an ultrasonic transducer array operatively connected to said means for producing an ultrasonic signal for transmitting said ultrasonic signal to a target said ultrasonic transducer array comprising;

(i) a connector having an upper surface, a lower surface, and an array of connector pads formed in said connector for electrically connecting said upper surface to said lower surface;

(ii) a piezoelectric transducer chip having a plurality of ultrasonic transducer elements arranged in a two-dimensional array, at least one of said ultrasonic transducer elements being a multilayer element having an internal edge portion and comprising a plurality of piezoelectric layers and a plurality of electrode layers forming a plurality of capacitative elements electrically connected in parallel, each of said plurality of piezoelectric layers being separated from the adjacent piezoelectric layers by one of said plurality of electrode layers, and said piezoelectric layers consisting of a first set of alternating electrode layers and a second set of alternating electrode layers interposed between said first set of alternating electrode layers;

(iii) a first via connecting said first set of alternating electrode layers, said first via being electrically insulated from said second set of alternating electrode layers; and

(iv) a second via connecting in parallel said second set of alternating electrode layers, said second via being electrically insulated from said first set of alternating electrode layers;

wherein at least one of said vias is an internal via;

(v) means for electrically connecting said first set of alternating electrodes to ground; and

(vi) means for electrically connecting said second set of alternating electrodes to a corresponding one of said connector pads;

(c) means for amplifying a received ultrasonic signal from a target operatively connected to said ultrasonic transducer array; and

(d) means for processing said ultrasonic signal operatively connected to said amplifying means.

17. An ultrasonic transducer array according to claim 16, which further comprises a metallic ground sheet which overlies said piezoelectric transducer chip and is electrically connected to said means for electrically connecting said first set of alternating electrodes.

18. An ultrasonic transducer array according to claim 16, wherein said means for electrically connecting said second set of alternating electrodes comprises a bonding layer to connect to said upper surface of said connector.

19. An ultrasonic transducer array according to claim 16, wherein said piezoelectric chip comprises a plurality of multilayer elements.

20. An ultrasonic transducer array according to claim 16, wherein said piezoelectric chip comprises at least one multilayer element which includes a first internal edge and a second internal edge, and wherein said first via is an internal via, and wherein said second via is an internal via.