Electrically adaptable neural network with post-processing circuitry

• US 5,331,215 A
• Filed: 07/30/1992
• Issued: 07/19/1994
• Est. Priority Date: 12/09/1988
• Status: Expired due to Term

• Current Assignee: Synaptics Incorporated
• Original Assignee: Synaptics Incorporated
• Inventors: Wall, Michael F., Allen, Timothy P., Platt, John C., Faggin, Federico, Mead, Carver A., Anderson, Janeen D. W.
• Primary Examiner(s): Westin, Edward P.
• Assistant Examiner(s): DRISCOLL, BENJAMIN
• Application Number:
  US07/922,535
• Time in Patent Office: 719 Days
• Field of Search: 307/201, 395/24
• US Class Current: 706/33
• CPC Class Codes: G06N 3/063 using electronic means
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H03F 1/0261 with control of the polarisation voltage or current, e.g. gliding Class A
• CPC Class Codes: H03F 1/303 using a switching device H03F1/305, H03F3/005, H03F3/38 take precedence
• CPC Class Codes: H03F 3/45479 characterised by the way of common mode signal rejection
• CPC Class Codes: H03F 3/45753 using switching means, e.g. sample and hold
• CPC Class Codes: H03F 3/45977 using switching means, e.g. sample and hold

Abstract

A synaptic array according to the present invention comprises a plurality of electrically-adaptable elements. Electrons may be placed onto and removed from a floating node in each electrically adaptable element associated with at least one MOS insulated gate field effect transistor, usually the gate of the transistor, in an analog manner, by application of first and second electrical control signals generated in response to an adapt signal. The inputs to all synaptic elements in a row are connected to a common row input line. Adapt inputs to all synaptic elements in a column are connected together to a common column adapt line. The current supplied to all amplifiers in a column is commonly provided by a sense line. In order to adapt the synaptic elements in the M row by N column matrix of the present invention, the voltages to which a given column n of the matrix is to be adapted are placed onto the input voltage lines, and the synaptic elements in column n are then simultaneously adapted by assertion of an adapt signal on the adapt line for column n. The vectors of input voltages for adapting successive columns may be placed sequentially onto the row input voltage lines and used to adapt the columns of synaptic elements by assertion of the adapt signals on the appropriate column adapt lines until the entire array is electrically adapted. After each synaptic element has been adapted, the current flowing through it will be maximized when the voltage at the input of the synaptic element equals the voltage to which the synaptic element has been adapted. An electrically adaptable winner-take-all circuit has its inputs connected to the column-sense lines of the array.

Claims

1. A synaptic array fabricated on a semiconductor substrate comprising:

a plurality of electrically-alterable synaptic elements disposed in at least one row and at least one column, each of said electrically-alterable synaptic elements comprising an input node, an output node, an amplifier having an input connected to a floating node and an output connected to said output node, a MOS capacitor having a first plate connected to said input node and a second plate connected to said floating node, an adapt control signal node, an electron injecting means coupled to said floating node for injecting electrons on to said floating node while the voltage on said floating node is within the normal operating range of said amplifier, negative feedback means, coupled between said floating node and said electron injecting means, and responsive to an adapt control signal asserted on said adapt control signal node for controlling said electron injecting means to vary the rate of injection of electrons on to said floating node in response to the magnitude of the voltage on said floating node, and a current sense node for supplying a current required by said synaptic element in response to a signal on said input node and said voltage on said floating node;

a row input line associated with each row of said array, each said row input line connected to the input nodes of all of said electrically alterable synaptic elements associated with its row;

at least one column sense line associated with each column of said array, each column sense line connected to the current sense nodes of all of said electrically alterable synaptic elements associated with its column;

a column adapt control input line associated with each column of said array, each said column adapt control input line connected to the adapt control signal nodes of all of said electrically alterable synaptic elements associated with its column, and

an electrically adaptable winner-take-all circuit having a plurality of corresponding inputs and outputs and an adapt input, a different one of said corresponding inputs connected to each one of said column sense lines.

2. The synaptic array of claim 1 wherein said electron injecting means is a semiconductor structure for performing hot electron injection.

3. The synaptic array of claim 2 wherein each of said electron injecting means is a non-avalanche hot electron injection device including:

a p-type region in said semiconductor substrate;

an n-type region disposed in said p-type region;

a floating gate disposed above said p-type region, said floating gate at least partially overlapping one edge of said n-type region and separated from the surface of said substrate by a gate oxide under a portion of said floating gate including at least where it partially overlaps the edge of said n-type region;

means for applying a first positive potential to said n-type region with respect to said p-type region to reverse bias said n-type region, said positive potential having a magnitude greater than about 2 volts relative to said p-type region, but less than the voltage required to induce avalanche breakdown between said n-type region and said p-type region;

means for capacitively coupling a second positive potential to said floating gate, said second positive potential having a magnitude of greater than about 2 volts relative to said p-type region;

means for injecting electrons into said p-type region;

whereby said first and second positive potentials act to accelerate said electrons to an energy sufficient to surmount the barrier energy of said gate oxide and thereby inject said electrons onto said floating gate.

4. A synaptic array fabricated on a semiconductor substrate comprising:

a plurality of electrically-alterable synaptic elements disposed in at least one row and at least two columns, each of said electrically-alterable synaptic elements comprising an input node, an output node, an amplifier having an input connected to a floating node and an output connected to said output node, an MOS capacitor having a first plate connected to said input node and a second plate connected to said floating node, an adapt control signal node, an electron removal means coupled to said floating node for removing electrons from said floating node while the voltage on said floating node is within the normal operating range of said amplifier, negative feedback means, coupled between said floating node and said electron removal means, and responsive to an adapt control signal asserted on said adapt control signal node for controlling said electron removal means to vary the rate of removal of electrons from said floating node in response to the magnitude of the voltage on said floating node, and a current sense node for supplying a current required by said synaptic element in response to a signal on said input node and said voltage on said floating node;

a row input line associated with each row of said array, each said row input line connected to the input nodes of all of said electrically alterable synaptic elements associated with its row;

a column sense line associated with each column of said array, each said column sense line connected to the current sense nodes of all of said electrically alterable synaptic elements associated with its column;

a column adapt control input line associated with each column of said array, each said column adapt control input line connected to the adapt control signal nodes of all of said electrically alterable synaptic elements associated with its column; and

an electrically adaptable winner-take-all circuit having a plurality of corresponding inputs and outputs and an adapt input, a different one of said corresponding inputs connected to each one of said column sense lines.

5. The synaptic array of claim 4 wherein said electron removal means is a conductor-insulator-conductor structure for performing electron tunneling.

6. The synaptic array of claim 5 wherein said floating node is a layer of polysilicon and said electron removal means includes a second layer of polysilicon separated from said floating node by a layer of SiO₂.

7. A synaptic array fabricated on a semiconductor substrate comprising:

a plurality of electrically-alterable synaptic elements disposed in at least one row and at least one column, each of said electrically-alterable synaptic elements comprising an input node, an output node, an amplifier having an input connected to a floating node and an output connected to said output node, an MOS capacitor having a first plate connected to said input node and a second plate connected to said floating node, an adapt control signal node, an electron injecting means coupled to said floating node for injecting electrons on to said floating node while the voltage on said floating node is within the normal operating range of said amplifier, electron removal means coupled to said floating node for removing electrons from said floating node while the voltage on said floating node is within the normal operating range of said amplifier, first negative feedback means coupled between said floating node and said electron injecting means, and responsive to an adapt control signal asserted on said adapt control signal node for controlling said electron injecting means to vary the rate of injection of electrons on to said floating node in response to the magnitude of the voltage on said floating node, second negative feedback means, coupled between said floating node and said electron removal means, and responsive to an adapt control signal asserted on said adapt control signal node for controlling said electron removal means to vary the rate of removal of electrons from said floating node in response to the magnitude of the voltage on said floating node, and a current sense node for supplying a current required by said Synaptic element in response to a signal on said input node and said voltage on said floating node;

a row input line associated with each row of said array, each said row input line connected to the input nodes of all of said electrically alterable synaptic elements associated with its row;

a column sense line associated with each column of said array, each said column sense line connected to the current sense nodes of all of said electrically alterable synaptic elements associated with its column;

a column adapt control input line associated with each column of said array, each said column adapt control input line connected to the adapt control signal nodes of all of said electrically alterable synaptic elements associated with its column; and

an electrically adaptable winner-take-all circuit having a plurality of corresponding inputs and outputs and an adapt input, a different one of said corresponding inputs connected to each one of said column sense lines.

8. The synaptic array of claim 7 wherein said electron injecting means is a conductor-insulator-conductor structure for performing hot electron injection.

9. The synaptic array of claim 8 wherein each of said electron injecting means is a semiconductor structure for performing non-avalanche hot electron injection including:

a p-type region in said semiconductor substrate;

an n-type region disposed in said p-type region;

a floating gate disposed above said p-type region, said floating gate at least partially overlapping one edge of said n-type region and separated from the surface of said substrate by a gate oxide under a portion of said floating gate including at least where it partially overlaps the edge of said n-type region;

means for applying a first positive potential to said n-type region with respect to said p-type region to reverse bias said n-type region, said positive potential having a magnitude greater than about 2 volts relative to said p-type region, but less than the voltage required to induce avalanche breakdown between said n-type region and said p-type region;

means for capacitively coupling a second positive potential to said floating gate, said second positive potential having a magnitude of greater than about 2 volts relative to said p-type region;

means for injecting electrons into said p-type region;

whereby said first and second positive potentials act to accelerate said electrons to an energy sufficient to surmount the barrier energy of said gate oxide and thereby inject said electrons onto said floating gate.

10. The synaptic array of claim 7 wherein said electron removal means is a conductor-insulator-conductor structure for performing electron tunneling.

11. The synaptic array of claim 10 wherein said floating node is a layer of polysilicon and said electron removal means includes a second layer of polysilicon separated from said floating node by a layer of SiO₂.

12. A synaptic array fabricated on a semiconductor substrate comprising:

a plurality of electrically-alterable synaptic elements disposed in at least one row and at least two columns, each of said electrically-alterable synaptic elements comprising an input node, an output node, an inverter including a P-Channel MOS transistor having a drain, a source connected to said current sense node, and a gate connected to a floating node,and an N-Channel MOS transistor having a drain connected to the drain of said P-Channel MOS transistor and to said output node, a gate connected to said floating node, and a source connected to a source of a fixed voltage potential, a MOS capacitor connected between said input node and said floating node, an adapt control signal node, an electron injecting means coupled to said floating node for injecting electrons on to said floating node while the voltage on said floating node is within the normal operating range of said inverter, injector control means, responsive to said adapt signal and the voltage on said output node, for generating an electrical injection control signal to control said electron injecting means to increase the rate of injection of electrons on to said floating node in response to an increase in voltage on said floating node and to decrease the rate of injection of electrons on to said floating node in response to an decrease in voltage on said floating node, and a current sense node for supplying a current required by said synaptic element in response to a signal on said input node and said voltage on said floating node;

a row input line associated with each row of said array, each said row input line connected to the input nodes of all of said electrically alterable synaptic elements associated with its row;

a column sense line associated with each column of said array, each said column sense line connected to the current sense nodes of all of said electrically alterable synaptic elements associated with its column;

a column adapt control input line associated with each column of said array, each said column adapt control input line connected to the adapt control signal nodes of all of said electrically alterable synaptic elements associated with its column; and

an electrically adaptable winner-take-all circuit having a plurality of corresponding inputs and outputs and an adapt input, a different one of said corresponding inputs connected to each one of said column sense lines.

13. The synaptic array of claim 12 wherein said electron injecting means is a conductor-insulator-conductor structure for performing hot electron injection.

14. The synaptic array of claim 13 wherein said electron injecting means is a non-avalanche hot electron injection device including:

a p-type region in said semiconductor substrate;

an n-type region disposed in said p-type region;

a floating gate disposed above said p-type region, said floating gate at least partially overlapping one edge of said n-type region and separated from the surface of said substrate by a gate oxide under a portion of said floating gate including at least where it partially overlaps the edge of said n-type region;

means for applying a first positive potential to said n-type region with respect to said p-type region to reverse bias said n-type region, said positive potential having a magnitude greater than about 2 volts relative to said p-type region, but less than the voltage required to induce avalanche breakdown between said n-type region and said p-type region;

means for capacitively coupling a second positive potential to said floating gate, said second positive potential having a magnitude of greater than about 2 volts relative to said p-type region;

means for injecting electrons into said p-type region;

whereby said first and second positive potentials act to accelerate said electrons to an energy sufficient to surmount the barrier energy of said gate oxide and thereby inject said electrons onto said floating gate.

15. A synaptic array fabricated on a semiconductor substrate comprising:

a plurality of electrically-alterable synaptic elements disposed in at least one row and at least one column, each of said electrically-alterable synaptic elements comprising an input node, an output node, an inverter including a P-Channel MOS transistor having a drain, a source connected to said current sense node, and a gate connected to a floating node,and an N-Channel MOS transistor having a drain connected to the drain of said P-Channel MOS transistor and to said output node, a gate connected to said floating node, and a source connected to a source of a fixed voltage potential, a MOS capacitor connected between said input node and said floating node, an adapt control signal node, an electron removal means coupled to said floating node for removing electrons from said floating node while the voltage on said floating node is within the normal operating range of said inverter, removal control means, responsive to said adapt signal and the voltage on said output node, for generating an electrical removal control signal to control said electron removal means to decrease the rate of removal of electrons on to said floating node in response to an increase in voltage on said floating node and to increase the rate of removal of electrons on to said floating node in response to an decrease in voltage on said floating node, and a current sense node for supplying a current required by said synaptic element in response to a Signal on said input node and said voltage on said floating node;

a row input line associated with each row of said array, each said row input line connected to the input nodes of all of said electrically alterable synaptic elements associated with its row;

a column sense line associated with each column of said array, each said column sense line connected to the current sense nodes of all of said electrically alterable synaptic elements associated with its column;

a column adapt control input line associated with each column of said array, each said column adapt control input line connected to the adapt control signal nodes of all of said electrically alterable synaptic elements associated with its column; and

an electrically adaptable winner-take-all circuit having a plurality of corresponding inputs and outputs and an adapt input, a different one of said corresponding inputs connected to each one of said column sense lines.

16. The synaptic array of claim 15 wherein said electron removal means is a conductor-insulator-conductor structure for performing electron tunneling.

17. The synaptic array of claim 16 wherein said floating node is a layer of polysilicon and said electron removal means includes a second layer of polysilicon separated from said floating node by a layer of SiO₂.

21. The synaptic array of claim 17 wherein said electron removal means is a conductor-insulator-conductor structure for performing electron tunneling.

22. The synaptic array of claim 21 wherein said floating node is a layer of polysilicon and said electron removal means includes a second layer of polysilicon separated from said floating node by a layer of SiO₂.

18. A synaptic array fabricated on a semiconductor substrate comprising:

a plurality of electrically-alterable synaptic elements disposed in at least one row and at least two columns, each of said electrically-alterable synaptic elements comprising an input node, an output node, an inverter including a P-Channel MOS transistor having a drain, a source connected to said current sense node, and a gate connected to a floating node,and an N-Channel MOS transistor having a drain connected to the drain of said P-Channel MOS transistor and to said output node, a gate connected to said floating node, and a source connected to a source of a fixed voltage potential, a MOS capacitor connected between said input node and said floating node, an adapt control signal node, an electron injecting means coupled to said floating node for injecting electrons on to said floating node while the voltage on said floating node is within the normal operating range of said inverter, electron removal means coupled to said floating node for removing electrons from said floating node while the voltage on said floating node is within the normal operating range of said inverter, injector control means, responsive to said adapt signal and the voltage on said output node, for generating an electrical injection control signal to control said electron injecting means to increase the rate of injection of electrons on to said floating node in response to an increase in voltage on said floating node and to decrease the rate of injection of electrons on to said floating node in response to an decrease in voltage on said floating node, removal control means, responsive to said adapt signal and the voltage on said output node, for generating an electrical removal control signal to control said electron removal means to decrease the rate of removal of electrons on to said floating node in response to an increase in voltage on said floating node and to increase the rate of removal of electrons on to said floating node in response to an decrease in voltage on said floating node, and a current sense node for Supplying a current required by said synaptic element in response to a signal on said input node and said voltage on said floating node;

a row input line associated with each row of said array, each said row input line connected to the input nodes of all of said electrically alterable synaptic elements associated with its row;

a column sense line associated with each column of said array, each said column sense line connected to the current sense nodes of all of said electrically alterable synaptic elements associated with its column;

a column adapt control input line associated with each column of said array, each said column adapt control input line connected to the adapt control signal nodes of all of said electrically alterable synaptic elements associated with its column; and

an electrically adaptable winner-take-all circuit having a plurality of corresponding inputs and outputs and an adapt input, a different one of said corresponding inputs connected to each one of said column sense lines.

19. The synaptic array of claim 18 wherein said electron injecting means is a conductor-insulator-conductor structure for performing hot electron injection.

20. The synaptic array of claim 19 wherein said electron injecting means is a non-avalanche hot electron injection device including:

a p-type region in said semiconductor substrate;

an n-type region disposed in said p-type region;

a floating gate disposed above said p-type region, said floating gate at least partially overlapping one edge of said n-type region and separated from the surface of said substrate by a gate oxide under a portion of said floating gate including at least where it partially overlaps the edge of said n-type region;

means for applying a first positive potential to said n-type region with respect to said p-type region to reverse bias said n-type region, said positive potential having a magnitude greater than about 2 volts relative to said p-type region, but less than the voltage required to induce avalanche breakdown between said n-type region and said p-type region;

means for capacitively coupling a second positive potential to said floating gate, said second positive potential having a magnitude of greater than about 2 volts relative to said p-type region;

means for injecting electrons into said p-type region;

whereby said first and second positive potentials act to accelerate said electrons to an energy sufficient to surmount the barrier energy of said gate oxide and thereby inject said electrons onto said floating gate.

23. A synaptic array fabricated on a semiconductor substrate comprising:

a plurality of electrically-alterable synaptic elements disposed in at least one row and at least one column, each of said electrically-alterable synaptic elements comprising an input node, an output node, an amplifier having an input connected to a floating node and an output connected to said output node, an MOS capacitor having a first plate connected to said input node and a second plate connected to said floating node, an adapt control signal node, an electron injecting means coupled to said floating node for injecting electrons on to said floating node while the voltage on said floating node is within the normal operating range of said amplifier, negative feedback means, coupled between said floating node and said electron injecting means, and responsive to an adapt control signal asserted on said adapt control signal node for controlling said electron injecting means to vary the rate of injection of electrons on to said floating node in response to the magnitude of the voltage on said floating node, and a current sense node for supplying a current required by said synaptic element in response to a signal on said input node and said voltage on said floating node;

a row input line associated with each row of said array, each said row input line connected to the input nodes of all of said electrically alterable synaptic elements associated with its row;

a column sense line associated with each column of said array, each said column sense line connected to the current sense nodes of all of said electrically alterable synaptic elements associated with its column; and

a column adapt control input line associated with each column of said array, each said column adapt control input line connected to the adapt control signal nodes of all of said electrically alterable synaptic elements associated with its column.

24. The synaptic array of claim 23 wherein said electron injecting means is a semiconductor structure for performing hot electron injection.

25. The synaptic array of claim 24 wherein each of said electron injecting means is a non-avalanche hot electron injection device including:

a p-type region in said semiconductor substrate;

an n-type region disposed in said p-type region;

a floating gate disposed above said p-type region, said floating gate at least partially overlapping one edge of said n-type region and separated from the surface of said substrate by a gate oxide under a portion of said floating gate including at least where it partially overlaps the edge of said n-type region;

means for applying a first positive potential to said n-type region with respect to said p-type region to reverse bias said n-type region, said positive potential having a magnitude greater than about 3.2 volts relative to said p-type region, but less than the voltage required to induce avalanche breakdown between said n-type region and said p-type region;

means for capacitively coupling a second positive potential to said floating gate, said second positive potential having a magnitude of greater than about 3.2 volts relative to said p-type region;

means for injecting electrons into said p-type region;

whereby said first and second positive potentials act to accelerate said electrons to an energy sufficient to surmount the barrier energy of said gate oxide and thereby inject said electrons onto said floating gate.

26. A synaptic array fabricated on a semiconductor substrate comprising:

a plurality of electrically-alterable synaptic elements disposed in at least one row and at least one column, each of said electrically-alterable synaptic elements comprising an input node, an output node, an amplifier having an input connected to a floating node and an output connected to said output node, an MOS capacitor having a first plate connected to said input node and a second plate connected to said floating node, an adapt control signal node, an electron removal means coupled to said floating node for removing electrons from said floating node while the voltage on said floating node is within the normal operating range of said amplifier, negative feedback means, coupled between said floating node and said electron removal means, and responsive to an adapt control signal asserted on said adapt control signal node for controlling said electron removal means to vary the rate of removal of electrons from said floating node in response to the magnitude of the voltage on said floating node, and a current sense node for supplying a current required by said synaptic element in response to a signal on said input node and said voltage on said floating node;

a row input line associated with each row of said array, each said row input line connected to the input nodes of all of said electrically alterable synaptic elements associated with its row;

a column sense line associated with each column of said array, each said column sense line connected to the current sense nodes of all of said electrically alterable synaptic elements associated with its column; and

a column adapt control input line associated with each column of said array, each said column adapt control input line connected to the adapt control signal nodes of all of said electrically alterable synaptic elements associated with its column.

27. The synaptic array of claim 26 wherein said electron removal means is a semiconductor structure for performing electron tunneling.

28. The synaptic array of claim 27 wherein said floating node is a layer of polysilicon and said electron removal means includes a second layer of polysilicon separated from said floating node by a layer of SiO₂.

29. A synaptic array fabricated on a semiconductor substrate comprising:

a plurality of electrically-alterable synaptic elements disposed in at least one row and at least one column, each of said electrically-alterable synaptic elements comprising an input node, an output node, an amplifier having an input connected to a floating node and an output connected to said output node, an MOS capacitor having a first plate connected to said input node and a second plate connected to said floating node, an adapt control signal node, an electron injecting means coupled to said floating node for injecting electrons on to said floating node while the voltage on said floating node is within the normal operating range of said amplifier, an electron removal means coupled to said floating node for removing electrons from said floating node while the voltage on said floating node is within the normal operating range of said amplifier, first negative feedback means coupled between said floating node and said electron injecting means, and responsive to an adapt control signal asserted on said adapt control signal node for controlling said electron injecting means to vary the rate of injection of electrons on to said floating node in response to the magnitude of the voltage on said floating node, second negative feedback means, coupled between said floating node and said electron removal means, and responsive to an adapt control signal asserted on said adapt control signal node for controlling said electron removal means to vary the rate of removal of electrons from said floating node in response to the magnitude of the voltage on said floating node, and a current sense node for supplying a current required by said synaptic element in response to a signal on said input node and said voltage on said floating node;

a row input line associated with each row of said array, each said row input line connected to the input nodes of all of said electrically alterable synaptic elements associated with its row;

a column sense line associated with each column of said array, each said column sense line connected to the current sense nodes of all of said electrically alterable synaptic elements associated with its column; and

a column adapt control input line associated with each column of said array, each said column adapt control input line connected to the adapt control signal nodes of all of said electrically alterable synaptic elements associated with its column.

30. The synaptic array of claim 29 wherein said electron injecting means is a semiconductor structure for performing hot electron injection.

31. The synaptic array of claim 30 wherein each of said electron injecting means is a semiconductor structure for performing non-avalanche hot electron injection including:

a p-type region in said semiconductor substrate;

an n-type region disposed in said p-type region;

a floating gate disposed above said p-type region, said floating gate at least partially overlapping one edge of said n-type region and separated from the surface of said substrate by a gate oxide under a portion of said floating gate including at least where it partially overlaps the edge of said n-type region;

means for applying a first positive potential to said n-type region with respect to said p-type region to reverse bias said n-type region, said positive potential having a magnitude greater than about 3.2 volts relative to said p-type region, but less than the voltage required to induce avalanche breakdown between said n-type region and said p-type region;

means for capacitively coupling a second positive potential to said floating gate, said second positive potential having a magnitude of greater than about 3.2 volts relative to said p-type region;

means for injecting electrons into said p-type region;

whereby said first and second positive potentials act to accelerate said electrons to an energy sufficient to surmount the barrier energy of said gate oxide and thereby inject said electrons onto said floating gate.

32. The synaptic array of claim 31 wherein said electron removal means is a semiconductor structure for performing electron tunneling.

33. The synaptic array of claim 32 wherein said floating node is a layer of polysilicon and said electron removal means includes a second layer of polysilicon separated from said floating node by a layer of SiO₂.

34. A synaptic array fabricated on a semiconductor substrate comprising:

a plurality of electrically-alterable synaptic elements disposed in at least one row and at least one column, each of said electrically-alterable synaptic elements comprising an input node, an output node, an inverter including a P-Channel MOS transistor having a drain, a source connected to said current sense node, and a gate connected to a floating node,and an N-Channel MOS transistor having a drain connected to the drain of said P-Channel MOS transistor and to said output node, a gate connected to said floating node, and a source connected to a source of a fixed voltage potential, a MOS capacitor connected between said input node and said floating node, an adapt control signal node, an electron injecting means coupled to said floating node for injecting electrons on to said floating node while the voltage on said floating node is within the normal operating range of said amplifier, injector control means, responsive to said adapt signal and the voltage on said output node, for generating an electrical injection control signal to control said electron injecting means to increase the rate of injection of electrons on to said floating node in response to an increase in voltage on said floating node and to decrease the rate of injection of electrons on to said floating node in response to an decrease in voltage on said floating node, and a current sense node for supplying a current required by said synaptic element in response to a signal on said input node and said voltage on said floating node;

a row input line associated with each row of said array, each said row input line connected to the input nodes of all of said electrically alterable synaptic elements associated with its row;

a column sense line associated with each column of said array, each said column sense line connected to the current sense nodes of all of said electrically alterable synaptic elements associated with its column; and

a column adapt control input line associated with each column of said array, each said column adapt control input line connected to the adapt control signal nodes of all of said electrically alterable synaptic elements associated with its column.

35. The synaptic array of claim 34 wherein said electron injecting means is a semiconductor structure for performing hot electron injection.

36. The synaptic array of claim 35 wherein said electron injecting means is a non-avalanche hot electron injection device including:

a p-type region in said semiconductor substrate;

an n-type region disposed in said p-type region;

a floating gate disposed above said p-type region, said floating gate at least partially overlapping one edge of said n-type region and separated from the surface of said substrate by a gate oxide under a portion of said floating gate including at least where it partially overlaps the edge of said n-type region;

means for applying a first positive potential to said n-type region with respect to said p-type region to reverse bias said n-type region, said positive potential having a magnitude greater than about 3.2 volts relative to said p-type region, but less than the voltage required to induce avalanche breakdown between said n-type region and said p-type region;

means for capacitively coupling a second positive potential to said floating gate, said second positive potential having a magnitude of greater than about 3.2 volts relative to said p-type region;

means for injecting electrons into said p-type region;

whereby said first and second positive potentials act to accelerate said electrons to an energy sufficient to surmount the barrier energy of said gate oxide and thereby inject said electrons onto said floating gate.

37. A synaptic array fabricated on a semiconductor substrate comprising:

a plurality of electrically-alterable synaptic elements disposed in at least one row and at least one column, each of said electrically-alterable synaptic elements comprising an input node, an output node, an inverter including a P-Channel MOS transistor having a drain, a source connected to said current sense node, and a gate connected to a floating node,and an N-Channel MOS transistor having a drain connected to the drain of said P-Channel MOS transistor and to said output node, a gate connected to said floating node, and a source connected to a source of a fixed voltage potential, a MOS capacitor connected between said input node and said floating node, an adapt control signal node, electron removal means coupled to said floating node for removing electrons from said floating node while the voltage on said floating node is within the normal operating range of said amplifier, removal control means, responsive to said adapt signal and the voltage on said output node, for generating an electrical removal control signal to control said electron removal means to decrease the rate of removal of electrons on to said floating node in response to an increase in voltage on said floating node and to increase the rate of removal of electrons on to said floating node in response to an decrease in voltage on said floating node, and a current sense node for supplying a current required by said synaptic element in response to a signal on said input node and said voltage on said floating node;

a row input line associated with each row of said array, each said row input line connected to the input nodes of all of said electrically alterable synaptic elements associated with its row;

a column sense line associated with each column of said array, each said column sense line connected to the current sense nodes of all of said electrically alterable synaptic elements associated with its column; and

a column adapt control input line associated with each column of said array, each said column adapt control input line connected to the adapt control signal nodes of all of said electrically alterable synaptic elements associated with its column.

38. The synaptic array of claim 37 wherein said electron removal means is a semiconductor structure for performing electron tunneling.

39. The synaptic array of claim 38 wherein said floating node is a layer of polysilicon and said electron removal means includes a second layer of polysilicon separated from said floating node by a layer of SiO₂.

43. The synaptic array of claim 39 wherein said electron removal means is a semiconductor structure for performing electron tunneling.

44. The synaptic array of claim 43 wherein said floating node is a layer of polysilicon and said electron removal means includes a second layer of polysilicon separated from said floating node by a layer of SiO₂.

40. A synaptic array fabricated on a semiconductor substrate comprising:

a plurality of electrically-alterable synaptic elements disposed in at least one row and at least one column, each of said electrically-alterable synaptic elements comprising an input node, an output node, an inverter including a P-Channel MOS transistor having a drain, a source connected to said current sense node, and a gate connected to a floating node,and an N-Channel MOS transistor having a drain connected to the drain of said P-Channel MOS transistor and to said output node, a gate connected to said floating node, and a source connected to a source of a fixed voltage potential, a MOS capacitor connected between said input node and said floating node, an adapt control signal node, an electron injecting means coupled to said floating node for injecting electrons on to said floating node while the voltage on said floating node is within the normal operating range of said amplifier, an electron removal means coupled to said floating node for removing electrons from said floating node while the voltage on said floating node is within the normal operating range of said amplifier, injector control means, responsive to said adapt signal and the voltage on said output node, for generating an electrical injection control signal to control said electron injecting means to increase the rate of injection of electrons on to said floating node in response to an increase in voltage on said floating node and to decrease the rate of injection of electrons on to said floating node in response to an decrease in voltage on said floating node, removal control means, responsive to said adapt signal and the voltage on said output node, for generating an electrical removal control signal to control said electron removal means to decrease the rate of removal of electrons on to said floating node in response to an increase in voltage on said floating node and to increase the rate of removal of electrons on to said floating node in response to an decrease in voltage on said floating node, and a current sense node for supplying a current required by said synaptic element in response to a signal on said input node and said voltage on said floating node;

a row input line associated with each row of said array, each said row input line connected to the input nodes of all of said electrically alterable synaptic elements associated with its row;

a column sense line associated with each column of said array, each said column sense line connected to the current sense nodes of all of said electrically alterable synaptic elements associated with its column; and

a column adapt control input line associated with each column of said array, each said column adapt control input line connected to the adapt control signal nodes of all of said electrically alterable synaptic elements associated with its column.

41. The synaptic array of claim 40 wherein said electron injecting means is a semiconductor structure for performing hot electron injection.

42. The synaptic array of claim 41 wherein said electron injecting means is a non-avalanche hot electron injection device including:

a p-type region in said semiconductor substrate;

an n-type region disposed in said p-type region;

a floating gate disposed above said p-type region, said floating gate at least partially overlapping one edge of said n-type region and separated from the surface of said substrate by a gate oxide under a portion of said floating gate including at least where it partially overlaps the edge of said n-type region;

means for applying a first positive potential to said n-type region with respect to said p-type region to reverse bias said n-type region, said positive potential having a magnitude greater than about 3.2 volts relative to said p-type region, but less than the voltage required to induce avalanche breakdown between said n-type region and said p-type region;

means for capacitively coupling a second positive potential to said floating gate, said second positive potential having a magnitude of greater than about 3.2 volts relative to said p-type region;

means for injecting electrons into said p-type region;

whereby said first and second positive potentials act to accelerate said electrons to an energy sufficient to surmount the barrier energy of said gate oxide and thereby inject said electrons onto said floating gate.