Discrete cosine transformation processor

• US 5,331,584 A
• Filed: 12/28/1992
• Issued: 07/19/1994
• Est. Priority Date: 12/27/1991
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Corporation
• Inventors: Sawada, Akira, Kitsuki, Toshiaki
• Primary Examiner(s): Mai, Tan V.
• Application Number:
  US07/997,326
• Time in Patent Office: 568 Days
• Field of Search: 364/725-727
• US Class Current: 708/402
• CPC Class Codes: G06F 17/147 Discrete orthonormal transforms, e.g. discrete cosine transform, discrete sine transform, and variations therefrom, e.g. modified discrete cosine transform, integer transforms approximating the discrete cosine transform G06F17/145 takes precedence

Abstract

A discrete cosine transformation processor subjects a plurality of input data to addition or subtraction at an adder/subtracter with two combinations according to the control signal every clock pulse so as to output a plurality of combination data. The combination data are assigned to eight groups according to certain combinations and each of them is input to one of eight selection circuits. The selection circuit selects one data from the combination input data according to the control signal and outputs the selected data every clock pulse. A multiplier receives the data selected by the selection circuit and multiplies it by a predetermined coefficient every clock pulse. Further, a second adder/subtracter subjects the output data from the multiplier to addition or subtraction in different combinations according to the control signal to determine cosine transformation coefficient to inverse cosine transformation coefficients.

Claims

1. A discrete cosine transformation processor to determine discrete cosine transformation coefficients and inverse cosine transformation coefficients based on input data comprising:

a first addition/subtraction means to subject a plurality of input data arranged to certain combinations to addition or subtraction according to a first control signal every clock so as to output a plurality of combination input data,

a plurality of selection means which receive the data from said first addition/subtraction means assigned to a plurality of groups according to certain combinations for data input group by group and output one of the combination input data according to a predetermined second control signal,

a plurality of multiplication means which respectively receive a plurality of selected data selected by said selection means and multiply the selected data by the predetermined coefficients, and

a plurality of second addition/subtraction means which perform addition or subtraction according to a third control signal every clock using the data output from said multiplication means with different combinations so as to determine cosine transformation coefficients or inverse cosine transformation coefficients.

2. A discrete cosine transformation processor of claim 1 wherein each of aid first, second and third control signals comprises two types of signals for cosine coefficient transformation and inverse cosine coefficient transformation and said first, second and third control signals being switchable for every clock.

3. A discrete cosine transformation processor to determine discrete cosine transformation coefficients and inverse cosine transformation coefficients based on input data comprising:

eight first addition/subtraction means which perform addition or subtraction of eight input data with two combinations every clock according to a first control signal so as to output nine combination input data, eight selection means which receive the data from said first addition/subtraction means assigned to eight groups according to certain combinations for data input group by group and select one of the combination input data every clock according to a predetermined second control signal for output,

seven multiplication means which respectively receive the data selected at said selection means and multiply the selected data by a predetermined coefficient every clock, and

five second addition/subtraction means which perform addition or subtraction according to a third control signal using the data output from said multiplication means with different combinations every clock so as to determine cosine transformation coefficients or inverse cosine transformation coefficients.

4. A discrete cosine transformation processor of claim 3 wherein three of said five second addition/subtraction means are used for cosine transformation and the remaining two are used for inverse cosine transformation.

5. A discrete cosine transformation processor of claim 3 wherein said first control signal to specify addition or subtraction at said first addition/subtraction means, said second control signal for said selection signal and said third control signal to specify addition or subtraction at said second addition/subtraction means are given for each clock so that eight cosine transformation coefficients or inverse cosine coefficients are determined.

6. A discrete cosine transformation processor of claim 3 wherein each of said first, second and third control signals comprises two types of signals for cosine coefficient transformation and inverse cosine coefficient transformation and is switchable for every clock.

7. A discrete cosine transformation processor to determine discrete cosine transformation coefficients and inverse cosine transformation processor comprising:

eight first addition/subtraction means which perform addition or subtraction of eight input data with two combinations every clock according to a first control signal so as to output eight combination input data, eight selection means which receive the data from said first addition/subtraction means assigned to four groups according to certain combinations for data input group by group and select one of the combination input data every clock according to a predetermined second control signal for output,

four multiplication means with two types of coefficients which respectively receive the data selected at said selection means and multiply the selected data every clock by a coefficient specified by a third control signal, and

five second addition/subtraction means which perform addition or subtraction according to a fourth control signal using the data output from said multiplication means with different combinations every clock so as to determine cosine transformation coefficients or inverse cosine transformation coefficients.

8. A discrete cosine transformation processor of claim 7 wherein two of said four second addition/subtraction means are used for cosine transformation and the remaining two are used for inverse transformation.

9. A discrete cosine transformation processor of claim 7 wherein the first control signal for said first addition/subtraction means, the second selection signal for said selection means, the third control signal to select either of the two coefficients at said predetermined coefficient multipliers and the fourth control signal to specify addition or subtraction at said addition/subtraction means are given for each clock so that eight cosine transformation coefficients or inverse cosine transformation coefficients are determined.

10. A discrete cosine transformation processor of claim 7 wherein each of said first, second, third and fourth control signals comprises two types of signals for cosine coefficient transformation and inverse cosine coefficient transformation and said first, second, third and fourth control signals being switchable for every clock.