One-transistor adaptable analog storage element and array

• US 5,336,936 A
• Filed: 05/06/1992
• Issued: 08/09/1994
• Est. Priority Date: 05/06/1992
• Status: Expired due to Term

• Current Assignee: Synaptics Incorporated
• Original Assignee: Synaptics Incorporated
• Inventors: Allen, Timothy P., Cser, James B.
• Primary Examiner(s): Westin, Edward P.
• Assistant Examiner(s): SANTAMAURO, JON P
• Application Number:
  US07/879,964
• Time in Patent Office: 825 Days
• Field of Search: 307/201, 307/529, 307/465, 307/450, 395/24, 365/185
• US Class Current: 365/185.03
• CPC Class Codes: G06N 3/063 using electronic means
• CPC Class Codes: G06N 3/065 Analogue means
• CPC Class Codes: G11C 27/005 with non-volatile charge storage, e.g. on floating gate or MNOS

Abstract

An analog storage array according to the present invention is disposed on a semiconductor substrate. The array is arranged as a plurality of rows and a plurality of columns and includes a plurality of N-channel MOS transistors disposed in the rows and columns in a p-well in the semiconductor substrate. Each of the MOS transistors includes a source, a drain, and a floating gate forming a tunneling junction with a tunneling electrode. An input line is associated with each of the rows in the array. Each input line is connected to the source of each of the N-channel MOS transistors disposed in the row with which the input line is associated. A bias line is associated with each of the rows in the array. Each bias line is capacitively coupled to the floating gate of each of the N-channel MOS transistors disposed in the row with which the bias line is associated. A tunnel line is associated with each of the columns in the array. Each tunnel line connected to the tunneling electrode of each of the N-channel MOS transistors disposed in the column with which the bias line is associated. A current-sum line is associated with each of the columns in the array. Each current-sum line is connected to the drain of each of the N-channel MOS transistors disposed in the column with which the bias line is associated. Circuitry is provided for forward biasing said p-well with respect to the substrate. Circuitry is provided for simultaneously driving a selected one of the bias lines low while driving a selected one of the tunnel lines high, for raising the floating gate voltage of the one of the N-channel MOS transistors common to the selected one of the bias lines and the selected one of the tunnel lines.

Claims

1. An analog storage array comprising a plurality of cells arranged as a plurality of rows and a plurality of columns, said array disposed on an n-type semiconductor substrate and including:

a p-type well disposed in said n-type substrate;

a plurality of N-channel MOS transistors disposed in said rows and columns in said p-type well of said n-type semiconductor substrate, a single one of said N-channel MOS transistors comprising each cell, each of said N-channel MOS transistors including a source, a drain, and a floating gate forming a tunneling junction with a tunneling electrode;

an input line associated with each of said rows, each input line connected to the source of each of the N-channel MOS transistors disposed in the row with which the input line is associated;

a bias line associated with each of said rows, each bias line capacitively coupled to the floating gate of each of the N-channel MOS transistors disposed in the row with which the bias line is associated;

a tunnel line associated with each of said columns, each tunnel line connected to the tunneling electrode of each of the N-channel MOS transistors disposed in the column with which the bias line is associated;

a current-sum line associated with each of said columns, each current-sum line connected to the drain of each of the N-channel MOS transistors disposed in the column with which the bias line is associated;

means for forward biasing said p-well with respect to said substrate in order to inject minority electrons into said p-well; and

means for selectively raising the drain and source voltages of a selected one of said N-channel floating gate transistors to accelerate the said injected minority electrons enough to enable them to migrate onto the floating gate of said selected one of said N-channel floating gate transistors; and

means for simultaneously driving a selected one of said bias lines low while driving a selected one of said tunnel lines high, for causing electron tunneling from the floating gate of the one of the N-channel MOS transistors common to said selected one of said bias lines and said selected one of said tunnel lines.

2. An analog storage array comprising a plurality of cells arranged as a plurality of rows and a plurality of columns, said array disposed on an n-type semiconductor substrate and including:

a p-type well disposed in said n-type substrate;

a plurality of N-channel MOS transistors disposed in said rows and columns in said p-type well of said n-type semiconductor substrate, a single, one of said N-channel MOS transistors comprising each cell, each of said N-channel MOS transistors including a source, a drain, and a floating gate forming a tunneling junction with a tunneling electrode;

an input line associated with each of said rows, each input line connected to the source of each of the N-channel MOS transistors disposed in the row with which the input line is associated;

a bias line associated with each of said rows, each bias line capacitively coupled to the floating gate of each of the N-channel MOS transistors disposed in the row with which the bias line is associated;

a tunnel line associated with each of said columns, each tunnel line connected to the tunneling electrode of each of the N-channel MOS transistors disposed in the column with which the bias line is associated;

a current-sum line associated with each of said columns, each current-sum line connected to the drain of each of the N-channel MOS transistors disposed in the column with which the bias line is associated;

means for forward biasing said p-well with respect to said substrate in order to inject minority electrons into said p-well; and

means for simultaneously raising the drain and source voltages of at least one of said N-channel floating gate transistors to accelerate the said injected minority electrons enough to enable them to migrate onto the floating gates of said at least one of N-channel floating gate transistors; and

means for simultaneously driving selected ones of said bias lines low while driving selected ones of said tunnel lines high, for causing electron tunneling from selected ones of the floating gates of said N-channel MOS transistors.