Regulated delay line

• US 5,338,990 A
• Filed: 02/19/1993
• Issued: 08/16/1994
• Est. Priority Date: 06/18/1991
• Status: Expired due to Fees

• Current Assignee: Brooktree Broadband Holding, Inc. (Synaptics Incorporated)
• Original Assignee: Brooktree Corporation (Rockwell Automation, Inc.)
• Inventors: Lou, Perry W.
• Primary Examiner(s): Callahan, Timothy P.
• Application Number:
  US08/019,784
• Time in Patent Office: 543 Days
• Field of Search: 328/55, 328/155, 328/63, 307/262, 307/269, 307/603
• US Class Current: 327/264
• CPC Class Codes: H03K 2005/00097 Avoiding variations of delay using feedback, e.g. controlled by a PLL
• CPC Class Codes: H03K 2005/00136 Avoiding asymmetry of delay for leading or trailing edge; Avoiding variations of delay due to threshold
• CPC Class Codes: H03K 5/131 Digitally controlled

Abstract

Three delay lines may have common characteristics. The first delay line delays the rising edge of an input signal and a first inverter inverts this signal to provide a falling edge. A second inverter inverts the rising edge of the input signal to produce a falling edge which is introduced to the second delay line in a second path with the second inverter. The signals from the two paths may be introduced to a comparator which produces a control signal having logic levels dependent upon the relative times that the falling edges occur for the signals in the two paths. For example, the control signal may have the first logic level when the falling edge occurs first in the first path and the control signal may have the second logic level when the falling edge occurs first in the second path. The voltage from a charge pump is adjusted in accordance with the logic level of the control signal. This voltage is introduced to the first and second delay lines to adjust their delay to minimize the time difference in the falling edges of the signals from these lines. This voltage is also introduced to the third delay line to adjust its delay in accordance with the adjustments in the delays in the first and second lines. In this way, the third delay line provides the same time for rising edges and falling edges in data signals introduced to the line.

Claims

1. In combination for use with input data having rising edges and falling edges to provide a symmetrical delay between the rising and falling edges,

a first delay line,

first means for providing an input signal having first and second logic levels,

second means including the first delay line for introducing the input signal to the first delay line for delay by the delay line and for then providing a first signal with the second logic level from the second means when the input signal has the first logic level,

a second delay line,

third means including the second delay line for introducing the input signal to the second means to provide a second signal with the second logic level when the input signal has the first logic level and for then providing a delay of the second signal with the second logic level by the second delay line,

fourth means responsive to the respective production by the second and third means of the first and second delayed signals with the second logic level for producing a control signal indicating the relative times of production of such first and second delayed signals with the second logic level by the second and third means, and

fifth means responsive to the control signal from the fourth means for providing respective adjustments by the second means and the third means in the delays in the first and second delay lines to minimize any difference between the relative times of production by the second and third means of the first and second delayed signals with the second logic level.

2. In a combination as set forth in claim 1 wherein

the fourth means produces the control signal with a first logic level when the second means produces the first delayed signal with the second logic level before the production of the second delayed signal with the second logic level by the third means and the fourth means produces the control signal with a second logic level when the third means produces the second delayed signal with the second logic level before the production of the first delayed signal with the second logic level by the second means and wherein

the fifth means provides respective adjustments by the second means and the third means in the delays in the first and second delay lines to the input signal in accordance with the first and second logic levels of the control signal from the fourth means.

3. In a combination as set forth in claim 1 wherein

the first and second delay lines have common characteristics, and

the fifth means introduces the control signal to the second means and the third means to provide respective adjustments in the delays in the first and second delay lines in accordance with the characteristics of such control signal.

4. In a combination as set forth in claim 3 wherein

the first means introduces the input signal to the second and third means and the second means delays the input signal in the first delay line and inverts the input signal after such delay and the third means inverts the input signal and then delay the inverted input signal in the second delay line after such inversion.

5. In combination for use with data having rising and falling edges to provide a symmetrical delay between the rising and falling edges in such data,

a first variable delay line,

a second variable delay line,

first means for providing an input signal having a rising edge to provide the input signal with a first logic level and having a falling edge to provide the input signal with a second logic level,

second means including the first variable delay line for initially inverting the input signal and then delaying the inverted input signal to provide a first signal with the second logic level, after a period of time dependent upon the delay in the first variable delay line, from the time that the input signal has the first logic level,

third means including the second variable delay line for initially delaying the input signal and then inverting the delayed input signal to provide a second signal with the second logic level after a period of time dependent upon the delay in the second variable delay line, from the time that the input signal has the first logic level, and

fourth means responsive to the relative times in the production of the second logic level in the first and second signals in the second means and the third means for providing respective adjustments in the response of the to obtain the second logic level in the input signal in the second means and the third means to occur at substantially the same time after the input signal has the first logic level.

6. In a combination as set forth in claim 5 wherein

the first and second variable delay lines have common characteristics and wherein

the fourth means introduces an adjustable voltage to second and third means to obtain an adjustment in the delays in the first and second variable delay lines for a substantially simultaneous occurrence of the second logic level in the first and second signals and wherein the fourth means produces the adjustable voltage in response to the relative times in the production of the second logic level in the first and second signals in the second means and the third means.

7. In a combination as set forth in claim 6, including,

a third variable delay line having common characteristics with the first and second variable delay lines,

fifth means for adjusting the delay in the third variable delay line, and

sixth means for introducing the adjustable voltage from the fourth means to the fifth means to obtain an adjustment in the delay in the third variable delay line in accordance with the adjustments in the delays in the first and second variable delay lines.

8. In a combination as set forth in claim 7, including,

the second means including a first inverter, and

the third means including a second inverter.

9. In a combination as set forth in claim 8 wherein

the first inverter inverts the input signal and introduces the inverted input signal to the first variable delay line and wherein

the second variable delay line delays the input signal and introduces the delayed input signal to the second inverter.