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Interface circuit for interfacing a peripheral device with a microprocessor operating in either a synchronous or an asynchronous mode

  • US 5,339,395 A
  • Filed: 09/17/1992
  • Issued: 08/16/1994
  • Est. Priority Date: 09/17/1992
  • Status: Expired due to Fees
First Claim
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1. An interface circuit for interfacing a peripheral device and a microprocessor to enable data transference between a microprocessor data bus and a memory location within the peripheral device, the interface circuit comprising:

  • means for selecting an operating mode for the interface circuit, the operating mode being one of a synchronous mode and an asynchronous mode, whereby the interface circuit is operated in a synchronous mode when the microprocessor utilizes synchronous bus control and in an asynchronous mode when the microprocessor utilizes asynchronous bus control;

    means for receiving a request for access to a peripheral memory location from the microprocessor;

    means for providing the peripheral device with an address specifying the peripheral memory location being requested for access by the microprocessor;

    means for receiving a clock signal from the microprocessor;

    a temporary data storage register for temporarily storing data receiving from the microprocessor and the peripheral device;

    means coupling the microprocessor data bus and the data storage register for data transference between the microprocessor data bus and the interface circuit;

    means coupling the peripheral device and the data storage register for data transference between the interface circuit and the peripheral memory location;

    means for receiving an indication from the peripheral device indicating that the peripheral device is engaged in transferring data between the data storage register and the peripheral memory location; and

    control means responsive to the interface operating mode, the clock signal, the request for access from the microprocessor, and the indication of engagement in data transference from the peripheral device, for separately timing and controlling (A) data transference between the microprocessor data bus and the data storage register, and (B) data transference between the data storage register and the peripheral memory location.

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