Basic cell for BiCMOS gate array
First Claim
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1. A cell for use in a mask programmable array comprising:
- one or more small size P-channel transistors;
two or more medium size P-channel transistors;
two or more small size N-channel transistors;
two or more medium size N-channel transistors; and
one or more large size N-channel transistors;
said medium size P-channel transistors having a channel width at least approximately twice the size of said small size P-channel transistors, said medium size N-channel transistors having a channel width at least approximately twice the size of said small size N-channel transistors, said channel width of said small size P-channel transistors being equal to or narrower than said channel width of said small size N-channel transistors, said large size N-channel transistors having a channel width larger than the channel width of said medium size N-channel transistors,gates of said one or more small size N-channel transistors being isolated from gates of said one or more small and medium size P-channel transistors,wherein said cell is one of a plurality of identical cells located within an interior of said mask programmable array.
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Abstract
An improved cell for use in a mask programmable gate array is disclosed herein. The preferred cell comprises two compute sections, each comprising two pairs of medium size P and N-channel transistors, two small N-channel transistors, and a single small P-channel transistor. Each cell also comprises a high efficiency drive section containing a single bipolar pull-up transistor, a large N-channel pull-down transistor, and a small P-channel transistor. By using this cell, an extremely high compute capability per die area is achieved.
86 Citations
42 Claims
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1. A cell for use in a mask programmable array comprising:
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one or more small size P-channel transistors; two or more medium size P-channel transistors; two or more small size N-channel transistors; two or more medium size N-channel transistors; and one or more large size N-channel transistors; said medium size P-channel transistors having a channel width at least approximately twice the size of said small size P-channel transistors, said medium size N-channel transistors having a channel width at least approximately twice the size of said small size N-channel transistors, said channel width of said small size P-channel transistors being equal to or narrower than said channel width of said small size N-channel transistors, said large size N-channel transistors having a channel width larger than the channel width of said medium size N-channel transistors, gates of said one or more small size N-channel transistors being isolated from gates of said one or more small and medium size P-channel transistors, wherein said cell is one of a plurality of identical cells located within an interior of said mask programmable array.
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2. In a programmed BiCMOS gate array containing a plurality of programmed BiCMOS cells, each of said BiCMOS cells comprising:
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a plurality of P-channel transistors; two or more sizes of N-channel transistors; and one or more NPN bipolar transistors, each of said one or more NPN bipolar transistors sharing an N-well with one or more of said P-channel transistors so that said NPN bipolar transistors may only be used as pull-up devices, said BiCMOS cells containing no PNP bipolar transistors, said BiCMOS cells being formed internal to said gate array. - View Dependent Claims (3, 4, 5)
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6. In a programmed BiCMOS gate array containing a plurality of programmed BiCMOS cells, each of said BiCMOS cells comprising:
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a plurality of P-channel transistors; a plurality of N-channel transistors; and one more more bipolar transistors, each of said one or more bipolar transistors sharing an N-well with one or more of said P-channel transistors as that said bipolar transistors may only be used as pull-up devices, wherein said plurality of P-channel transistors comprises two or more sizes of P-channel transistors, where a size corresponds to a channel width, wherein said plurality of N-channel transistors comprise three or more sizes of N-channel transistors, where a size corresponds to a channel width, and wherein said cells are internal to said gate array. - View Dependent Claims (7, 8)
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- 9. An integrated circuit containing an array of programmed BiCMOS cells, one or more said cells comprising one or more substantially rectangular compute sections and one or more drive sections, each drive section comprising one or more bipolar transistors for use as pull-up devices in one or more macrocells, and one or more N-channel transistors for use as pull-down devices in said one or more macrocells for driving an output of said one or more macrocells to a low state, each compute section comprising components which may be interconnected to form a two-to-one multiplexer, said multiplexer having true and complement outputs, said true output being equal to a power supply voltage, said complement output being equal to ground potential.
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19. In a programmed gate array containing a plurality of programmed cells, each of said cells comprising;
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one or more substantially rectangular compute sections and one or more drive sections, each of said drive sections containing one or more MOS transistors which are substantially larger than MOS transistors within said compute sections, each compute section comprising; two or more sizes of P-channel transistors, where a size corresponds to a channel width; and two or more sizes of N-channel transistors; wherein said P-channel transistors comprise at least two medium size P-channel transistors and at least one small size P-channel transistors, wherein said small size P-channel transistor is smaller than each of said medium size P-channel transistor; and said N-channel transistors comprise at least two small size N-channel transistors and at least two medium size N-channel transistors, wherein each of said small size N-channel transistors has a greater current handling capability than each of said at least two medium size P-channel transistors, and wherein each of said medium size N-channel transistors is larger than each of said small size N-channel transistors. - View Dependent Claims (20, 21, 22, 23, 24, 25, 26, 27, 28)
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29. In a programmed BiCMOS gate array, one or more macrocells having one or more bipolar transistors being used as pull-up devices and no bipolar transistors being used as pull-down devices, wherein said pull-up devices are for driving an output of said one or more macrocells to a high state,
wherein said one or more macrocells are formed by the interconnection of components within one or more BICMOS cells in an unprogrammed BiCMOS gate array, each of said BiCMOS cells comprising one or more compute sections and one or more drive sections, each of said one or more drive sections including said one or more bipolar transistors, and each of said compute sections comprising a plurality of P-channel transistors, a plural of N-channel transistors, and no bipolar transistors.
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31. In a programmed BiCMOS gate array, one or more macrocells having one or more bipolar transistors being used as pull-up devices and no bipolar transistors being used as pull-down devices, wherein said pull-up devices are for driving an output of said one or more macrocells to a high state,
wherein said one or more macrocells are formed by the interconnection of components within one or more BiCMOS cells in an unprogrammed BiCMOS gate array, each of said BiCMOS cells comprising one or more substantially rectangular compute sections and one or more drive sections, each of said drive sections comprising: one or more bipolar transistors for use as pull-up devices in said one or more macrocells for driving an output of said one or more macrocells to a high state, and one or more N-channel transistors for use as pull-down devices in said one or more macrocells for driving an output of said one or more macrocells to a low state. - View Dependent Claims (32, 33, 34)
- 35. An integrated circuit containing an array of unprogrammed BiCMOS cells, one or more of said cells comprising one or more substantially rectangular compute sections and one or more drive sections, each drive section comprising three or more drive transistors for use as drive transistors in a single macrocell, said three or more drive transistors being programmably connectable so as to provide said macrocell with a variety of pull-up or pull-down driving capabilities.
Specification