Apparatus and method for ensuring that lock requests are serviced in a multiprocessor system

• US 5,341,491 A
• Filed: 10/22/1993
• Issued: 08/23/1994
• Est. Priority Date: 06/29/1990
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Digital Equipment Corporation (HP Inc.)
• Inventors: Ramanujan, Raj
• Primary Examiner(s): Dixon, Joseph L.
• Assistant Examiner(s): Nguyen, Hiep T.
• Application Number:
  US08/141,427
• Time in Patent Office: 305 Days
• Field of Search: 395/400, 395/425, 364/200 MS File, 364/900 MS File
• US Class Current: 711/152
• CPC Class Codes: G06F 9/524 Deadlock detection or avoidance

Abstract

A lockout avoidance circuit is provided for a plurality of nodes which generate lock requests for a shared resource such as a memory location. The circuit insures that lock requests are eventually satisfied. A lock queue includes a plurality of registers pipelined together. Lock requests only enter the lock queue if they are refused access to a shared resource a predetermined number of times. A first register is the head of the queue and the last register is the bottom of the queue. An enabling circuit allows the queue to store in the registers lock requests received from the different nodes in the order in which they are initially refused service. The enabling circuit operates the queue by pushing the stored lock requests toward the head of the queue each time the head entry in the queue is serviced. The lockout avoidance circuit is implemented at each level of the system wherein a lockout condition can occur.

Claims

1. A lockout avoidance circuit for a plurality of nodes generating lock requests for a shared resource, comprising

a queue including:

a plurality of registers pipelined together, a first of said registers being the head of the queue and the last of said registers being the tail of the queue;

means for counting lock requests that have been refused from at least one of said nodes;

means for enabling said queue to store a lock request from said node at the tail of the queue after a predetermined number of lock requests from said node have been refused and storing all subsequent lock requests from any other of said nodes at the tail of the queue in the order in which they are registered; and

said means for enabling operating said queue to advance the stored lock requests toward the head of said queue each time the lock request at the head of the queue is serviced.

2. A lockout avoidance circuit according to claim 1, wherein:

the means for counting refused lock requests comprises a plurality of counters coupled to said means for enabling, each one of said counters being associated with one of said nodes;

a count signal is provided to said means for enabling from one of said counters in response to the counter having reached a predetermined number of refused lock requests; and

said means for enabling stores a particular lock request from one of said nodes in the queue in response to the count signal associated with said node.

3. A lockout avoidance circuit according to claim 2 further comprising means for storing all subsequent lock requests from any of said nodes in the queue after the means for enabling has received the count signal from a counter.

4. A lockout avoidance circuit according to claim 3 wherein each of said registers comprises:

a valid indication field; and

a node source ID field.

5. A method for avoiding lockout of lock requests for a particular resource in a system, said lock requests generated from a plurality of nodes coupled to a central location, the method comprising the steps of:

counting at a central location the number of times a particular node is refused a lock request to a particular resource;

storing all lock requests for any system resource subsequent to a predetermined number of lock requests from the particular node that have been refused; and

servicing, serially in the order stored, all lock requests until all lock requests are satisfied.

6. A method for avoiding lockout of lock requests generated from a plurality of nodes coupled to a central location, the method comprising the steps of:

incrementing a counter associated with a particular one of the nodes when a lock request from said particular node is refused in the central location;

generating an end of count signal from said counter when the lock request is refused a predetermined number of times;

storing the lock request as a head entry in a queue once the end of count signal is generated;

subsequently storing any further lock requests from different nodes as further entries in said queue once the queue contains a head entry; and

operating said queue to the entries in the order in which they are placed in the queue.

7. A method according to claim 6 wherein the step of storing the lock request comprises generating a first signal to enable a first register in said queue to store the lock request.

8. A method according to claim 7 wherein the step of subsequently storing comprises generating a second signal to enable a next register in said queue to store the next lock request from a different node.

9. A method according to claim 8 wherein the step of operating the queue comprises:

generating a third signal to push said queue once the head entry is serviced such that the next entry in the queue becomes the head entry; and

continuing to generate the third signal each time the head entry is serviced until the queue is empty.

10. A method according to claim 9 wherein the step of operating said queue is carried out by a control circuit.

11. An apparatus for avoiding lockouts of lock requests in a multi-level hierarchical system, comprising:

a first lockout avoidance circuit in the highest hierarchical level of said system, said first lockout avoidance circuit guaranteeing that no lockout occurs for lock requests received at said highest hierarchical level, said first lockout avoidance circuit including;

a) first means for providing a first level lock request refusal signal if a predetermined number of lock request refusals occur, and

b) a first level lock queue for storing highest hierarchical level requester information in response to said first level lock request refusal signal; and

a second lockout avoidance circuit in the next highest hierarchical level of the system, said second lockout avoidance circuit guaranteeing that no lockouts occur at the next highest level, said second lockout avoidance circuit including;

a) second means for providing a second level lock request refusal signal if second level lock request refusals occur, and

b) a second level lock queue for storing next highest hierarchical level requester information in response to said second level lock request refusal signal.

12. A method for avoiding lockouts of lock requests in a multi-level hierarchical system, comprising the steps of:

operating a first lockout avoidance circuit in the highest hierarchical level of said system, said first lockout avoidance circuit guaranteeing that no lockout occurs for lock requests received at said highest hierarchical level and including the steps of;

a) providing a first level lock request refusal signal if a predetermined number of first level lock request refusals occurs, and

b) storing highest hierarchical level requester information in a first level lock queue in response to said first level lock request refusal signal; and

operating a second lockout avoidance circuit located in the next highest hierarchical level of the system, said second lockout avoidance circuit guaranteeing that no lockouts occur at the next highest hierarchical level and including the steps of;

a) providing a second level lock request refusal signal if second level lock request refusals occur, and

b) storing next highest hierarchical level requester information in a second level lock queue in response to said second level lock request refusal signal.

13. A circuit for servicing lock requests for memory locations generated from a plurality of nodes, comprising:

a plurality of lock registers, each of the lock registers including a storage device and a comparator having first and second inputs, said lock requests being provided to the first input of the comparator and to an input of the storage device, an output of the storage device being coupled to the second input of the comparator;

a lock queue coupled to said lock registers, the lock queue receiving lock requests at its inputs, the lock queue including a plurality of queue registers;

a control circuit coupled to the lock registers and lock queue for controlling the circuit operation;

a plurality of counters each providing a count signal to the control circuit, the number of counters and queue registers equalling the number of nodes from which lock requests are generated;

said control circuit including

a first signal for operating the lock registers;

a second signal for operating the lock queue; and

a third signal for operating the counters.

14. A circuit according to claim 13 wherein said lock queue further comprises:

a plurality of multiplexers, one of the multiplexers being associated with each one of the queue registers, said multiplexers receiving the second signal for operating the lock queue.

15. A circuit according to claim 14 wherein the plurality of lock registers provide either a lock refused or lock miss signal in response to a lock request;

and

the lock miss signal being forwarded .to the control circuit to activate the first signal for storing the lock request.

16. A circuit according to claim 15 wherein the lock refused signal enables the control circuit to generate the third signal to the respective counter associated with the node generating the lock request.

17. A circuit according to claim 16 wherein the counters are set to a predetermined value, said third signal incrementing the respective counter.

18. A circuit according to claim 17 comprising:

an end of count signal output from said counters once they reach their predetermined value, the end of count signal provided to the control circuit to activate the second signal.

19. A circuit according to claim 18 wherein each queue register comprises:

a valid indication field; and

a node source ID field.

20. A circuit according to claim 19 wherein each storage device includes:

an address field;

a node source ID field; and

a valid indicator.

21. A circuit according to claim 20 wherein the first signal selectively sets and clears the valid indicator.

22. A lockout avoidance circuit for a plurality of nodes generating lock requests for a shared resource, comprising:

a queue having a head and a tail;

means for counting lock requests that have been refused from at least one of the nodes;

means for enabling the queue to store a lock request from the node at the tail of the queue after a predetermined number of lock requests from the node have been refused, and storing all subsequent lock requests from any other of the nodes at the tail of the queue in the order in which they are requested;

the means for enabling operating the queue to advance the stored lock requests toward the head of the queue each time the lock request at the head of the queue is serviced.