Method of fabricating integrated circuit module

• US 5,341,564 A
• Filed: 05/10/1993
• Issued: 08/30/1994
• Est. Priority Date: 03/24/1992
• Status: Expired due to Fees

• Current Assignee: Unisys Corporation
• Original Assignee: Unisys Corporation
• Inventors: Economy, Ken W., Akhavain, Mohammad
• Primary Examiner(s): Arbes, Carl J.
• Application Number:
  US08/060,689
• Time in Patent Office: 477 Days
• Field of Search: 29/827, 29/832, 29/840, 437/183, 174/52.2, 174/52.4
• US Class Current: 29/832
• CPC Class Codes: H01L 2224/10135 Alignment aids
• CPC Class Codes: H01L 2224/10165 Alignment aids
• CPC Class Codes: H01L 2224/10175 Flow barriers
• CPC Class Codes: H01L 2224/16111 the bump connector being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/16237 the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/8014 Guiding structures outside the body
• CPC Class Codes: H01L 2224/81136 involving guiding structures, e.g. spacers or supporting members
• CPC Class Codes: H01L 2224/81139 Guiding structures on the body
• CPC Class Codes: H01L 2224/8114 Guiding structures outside the body
• CPC Class Codes: H01L 2224/81141 Guiding structures both on and outside the body
• CPC Class Codes: H01L 2224/81193 wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01057 Lanthanum [La]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15312 : being a pin array, e.g. PGA
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: Y10T 29/4913 : Assembling to base an electrical component, e.g., capacitor, etc.
• CPC Class Codes: Y10T 29/49144 : by metal fusion

Abstract

An integrated circuit module having microscopic self-alignment features comprises: 1) an integrated circuit chip having a plurality of input/output pads in a pattern on a surface thereof; 2) an interconnect member having a surface which includes input/output pads in a pattern that matches the pattern of pads on the integrated circuit chip; and, 3) one of the surfaces has a predetermined number of holes of one-half to fifty mils deep and the other surface has a predetermined number of protrusions of one-half to fifty mils high which are shaped to fit into the holes and prevent the surfaces from sliding on each other when the input/output pads on both of the surfaces are aligned.

Claims

1. A method of fabricating an integrated circuit module which comprises - a) an integrated circuit chip having a plurality of input/output pads in a pattern on a surface thereof, and b) an interconnect member having a surface with input/output pads in a pattern that matches said pattern of pads on said integrated circuit chip;

said method including the steps of;

forming an electrical insulating layer on one of said surfaces with a predetermined number of holes with vertical sidewalls which encompass said pads on said one surface, and forming a single solder ball on each of said pads on the other surface;

randomly placing said solder balls in contact with said insulating layer such that said matching patterns of input/output pads are randomly misaligned with each other; and

,

sliding said surface with said solder balls parallel to said insulating layer, in random directions, until said solder balls drop into said holes of said insulating layer.

2. A method according to claim 1 wherein said one surface has multiple holes and said other surface has a single respective solder ball for each hole.

3. A method according to claim 1 wherein said one surface has multiple holes and said other surface has a respective group of several solder balls for each hole.

4. A method according to claim 1 wherein said one surface has just a single hole and said other surface has multiple solder balls all of which fit into said single hole.

5. A method according to claim 1 wherein said insulating layer with said holes is on said interconnect member, and said solder balls are on said integrated circuit chip.

6. A method according to claim 1 wherein said insulating layer with said holes is on said integrated circuit chip, and said solder balls are on said interconnect member.

7. A method according to claim 1 wherein said holes in said insulating layer are partially filled with solder.

8. A method according to claim 1 wherein said holes are one-half to fifty mils deep and said solder balls are one-half to fifty mils high.

9. A method according to claim 1 wherein said holes are defined by a patterned layer of material selected from photoresist, polyimide, silicon dioxide, silicon nitride, and ceramic.