Microstepping bipolar stepping motor controller for document positioning

• US 5,359,271 A
• Filed: 01/25/1993
• Issued: 10/25/1994
• Est. Priority Date: 01/25/1993
• Status: Expired due to Term

• Current Assignee: Gtech Servicios de México, S. de R.L. de C.V.
• Original Assignee: GTECH Corporation (GTECH SpA)
• Inventors: Husher, Frederick K.
• Primary Examiner(s): SALATA, ANTHONY J
• Application Number:
  US08/008,187
• Time in Patent Office: 638 Days
• Field of Search: 318/696, 318/685, 318/61, 318/64, 318/270, 318/271, 271/3, 271/226, 271/254
• US Class Current: 318/696
• CPC Class Codes: H02P 8/22 Control of step size; Intermediate stepping, e.g. microstepping

Abstract

A controller for operating a stepping motor to a resolution defined by plural inter-pole motor positions includes a digital processor for communication with an external host system for controlling operation of the stepping motor, at least in a microstep mode. The processor selects Sine/Cosine driving current values for the motor windings from a table covering at least 90°, to define the inter-pole positions, stored in a RAMDAC or combination digital memory and digital to analog converter. The processor also controls scaling of the output of the digital to analog converter for different modes of operation, such as normal, hold and shutdown. The RAMDAC also can be loaded by the processor. Power stages are coupled to two analog outputs of the RAMDAC amplify the RAMDAC output signals, and provide a high power output to the windings using bridge drivers. The bridge drivers are enabled by analog comparators responsive to the analog input and to a current sense feedback, for enabling the bridge drivers until motor coil current reaches the value defined by the analog input, whereupon the driver is disabled and a one-shot is triggered to lock out the driver for preventing current overshoot.

Claims

1. A controller for operating a stepping motor having a plurality of motor coils and defining rotor and stator poles, the controller comprising:

at least one processor having control inputs for receiving operational commands, data and program memory means including random access memory for storage of information defining at least one stepping motor operation;

a digital memory addressable by the processor and a digital to analog converter coupled to an output of the digital memory, the digital memory storing data values representing sinusoidally varying current levels in the motor coils over at least 90°

of a passage of rotor and stator poles, and the digital to analog converter being operable to convert data values selected in the digital memory by the processor to analog levels simultaneously for a plurality of outputs of the digital to analog converter at least equal in number to the motor coils;

a plurality of power stages coupled to said outputs of the digital to analog converter and operable to produce currents in the motor coils corresponding to the analog levels; and

,

wherein the processor is operable selectively to read out the data values in the digital memory for accomplishing the stepping motor operation.

2. The controller according to claim 1, wherein the digital memory and digital to analog converter are provided in a RAMDAC having a reference input and means for scaling the output of the digital to analog converter as a function of the reference input, the RAMDAC providing said plurality of outputs of the digital to analog converter.

3. The controller according to claim 2, further comprising switching means coupled to the processor and to the reference input, the switching means being operable to adjust a level of the reference input for switching between stepping motor operations requiring distinct maximum levels of currents in the motor coils.

4. The controller according to claim 3, wherein the distinct maximum levels include higher maximum levels for normal operation and a Sine/Cosine maintained ratio of lower maximum levels for a hold operation.

5. The controller according to claim 4, wherein the distinct maximum levels include a substantially zero level for a shutdown operation.

6. The controller according to claim 3, wherein the reference input is a current input and further comprising a regulator coupled to the reference input and arranged normally to conduct a predetermined current value, and wherein the switching means comprises at least one current source switchably coupled to the reference input and to the regulator, for altering current at the reference input.

7. The controller according to claim 3, wherein the reference input is a current applied to an output stage of the digital to analog converter, and wherein the switching means is arranged to reverse bias the output stage for disabling operation in a shutdown mode of the controller.

8. The controller according to claim 2, wherein the power stages each comprise a comparator and a driver responsive to the comparator, a drive current level produced in a respective one of the motor coils being sensed and fed back to one input of the comparator, and an analog level from the RAMDAC being coupled to another input of the comparator, such that the comparator energizes the driver until the drive current level reaches the analog level from the RAMDAC.

9. The controller according to claim 8, further comprising a one-shot coupled to an output of the comparator and to the driver, the one-shot being operable to disable the driver for a predetermined period following a time at which the drive current level reaches the analog level.

11. The controller according to claim 9, wherein the driver comprises a bridge driver coupled to a power supply by a charge storage filter including a capacitor in parallel with the bridge driver and a resistor in series with the power supply.

12. The controller according to claim 1, wherein the processor is operable to choose among and to initiate said operation according to stored parameters determining at least one of maximum stepping motor speed, velocity profile pattern for ramp up and ramp down and variation of a type of step operation.

13. The controller according to claim 2, further comprising means for downloading the data values from the processor to the RAMDAC.

10. A controller for operating a stepping motor having a plurality of motor coils and defining rotor and stator poles, the controller comprising:

at least one processor having control inputs for receiving operational commands, data and program memory means including random access memory for storage of information defining at least one stepping motor operation;

a digital memory addressable by the processor and a digital to analog converter coupled to an output of the digital memory, the digital memory storing data values representing sinusoidally varying current levels in the motor coils over at least 90°

of a passage of rotor and stator poles, and the digital to analog converter being operable to convert data values selected in the digital memory by the processor to analog levels simultaneously for a plurality of outputs of the digital to analog converter at least equal in number to the motor coils;

a plurality of power stages coupled to said outputs of the digital to analog converter and operable to produce currents in the motor coils corresponding to the analog levels, the power stages each comprising a comparator and a driver responsive to the comparator, a drive current level produced in a respective one of the motor coils being sensed and fed back to one input of the comparator, and an analog level from the RAMDAC being coupled to another input of the comparator, such that the comparator energizes the driver until the drive current level reaches the analog level from the RAMDAC;

means coupled to an output of the comparator and to the driver, operable to disable the driver for a predetermined period following a time at which the drive current level reaches the analog level; and

,

wherein the driver comprises a bridge driver having phase control inputs coupled to outputs of the processor, and operable for reversing an output polarity of the bridge driver.