Highly stable asymmetric SRAM cell

• US 5,363,328 A
• Filed: 06/01/1993
• Issued: 11/08/1994
• Est. Priority Date: 06/01/1993
• Status: Expired due to Fees

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Browning, Clyde H. III, Longwell, Michael L.
• Primary Examiner(s): LaRoche, Eugene R.
• Assistant Examiner(s): NIRANJAN, FRANK
• Application Number:
  US08/069,325
• Time in Patent Office: 525 Days
• Field of Search: 365/154, 365/181, 365/189.07
• US Class Current: 365/154
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: H10B 10/15 comprising a resistor load element

Abstract

An asymmetric static random access memory cell (50 and 53) includes polysilicon load elements (55 and 56), N-channel pull-down transistors (57 and 58), and N-channel coupling transistors (59 and 60). One of the coupling transistors (59 and 81) has a channel width that is less than the channel width of the other coupling transistor (60 and 80). The asymmetric cells (50 and 53) are located close to power supply voltage terminal V_SS, while conventional symmetrical cells (51 and 52) are located apart from the power supply voltage terminal V_SS. The asymmetric cells (50 and 53) correct an imbalance in the ground path caused by a parasitic resistance (83 and 86) of a diffusion layer (94) that is used to couple the asymmetric cells (50 and 53) to ground potential. The asymmetric cell (50 and 53) improves cell stability without degrading performance or increasing cell area.

Claims

1. An asymmetric static random access memory cell, comprising:

a first load element having a first terminal connected to a first power supply voltage terminal, and a second terminal;

a second load element having a first terminal connected to the first power supply voltage terminal, and a second terminal;

a first pull-down transistor having a first current electrode coupled to the second terminal of the first load element, a second current electrode coupled to a second power supply voltage terminal, and a control electrode;

a second pull-down transistor having a first current electrode coupled to the second terminal of the second load element, a second current electrode coupled to the second power supply voltage terminal, and a control electrode;

a first coupling transistor having a first current electrode coupled to the first current electrode of the second pull-down transistor, a control electrode, and a second current electrode, the first coupling transistor having a first channel width; and

a second coupling transistor having a first current electrode coupled to the first current electrode of the first pull-down transistor, a control electrode, and a second current electrode, the second coupling transistor having a second channel width;

wherein the first channel width is less than the second channel width.

2. The asymmetric static random access memory cell of claim 1, wherein the first and second load elements are characterized as being polysilicon load resistors.

3. The asymmetric static random access memory cell of claim 1, wherein the first and second pull-down transistors and the first and second coupling transistors are N-channel MOS transistors.

4. The asymmetric static random access memory cell of claim 1, wherein the first coupling transistor has a first channel length and the second coupling transistor has a second channel length, the first and second channel lengths being substantially equal.

5. The asymmetric static random access memory cell of claim 1, wherein the gates of the first and second coupling transistors and the gates of the first and second pull-down transistors are formed in a first polysilicon layer.

6. The asymmetric static random access memory cell of claim 5, wherein the first and second load elements are formed in a second polysilicon layer.

7. An asymmetric static random access memory cell, comprising:

a first load element having a first terminal connected to a first power supply voltage terminal, and a second terminal;

a second load element having a first terminal connected to the first power supply voltage terminal, and a second terminal;

a first pull-down transistor having a first current electrode coupled to the second terminal of the first load element, a second current electrode coupled to a second power supply voltage terminal, and a control electrode;

a second pull-down transistor having a first current electrode coupled to the second terminal of the second load element, a second current electrode coupled to the second power supply voltage terminal, and a control electrode;

a first coupling transistor having a first current electrode coupled to the first current electrode of the second pull-down transistor, a control electrode, and a second current electrode, the first coupling transistor having a first channel width-to-channel length ratio; and

a second coupling transistor having a first current electrode coupled to the first current electrode of the first pull-down transistor, a control electrode, and a second current electrode, the second coupling transistor having a second channel width-to-channel length ratio;

wherein the first channel width-to-channel length ratio being less than the second channel width-to-channel length ratio.

8. The asymmetric static random access memory cell of claim 7, wherein the first and second load elements are characterized as being ion-implanted polysilicon load resistors.

9. The asymmetric static random access memory cell of claim 7, wherein the first and second pull-down transistors and the first and second coupling transistors are N-channel MOS transistors.

10. The asymmetric static random access memory cell of claim 7, wherein the gates of the first and second coupling transistors and the gates of the first and second pull-down transistors are formed in a first polysilicon layer.

11. The asymmetric static random access memory cell of claim 10, wherein the first and second load elements are formed in a second polysilicon layer.

12. A static random access memory array, comprising:

a plurality of words lines;

a plurality of bit line pairs arranged to intersect the plurality of word lines;

a power supply voltage terminal;

a first plurality of static random access memory cells coupled to the power supply voltage terminal, a memory cell of the first plurality of static random access memory cells having a first storage node coupled to a first bit line of a first bit line pair by a first coupling transistor, and a second storage node coupled to a second bit line of the first bit line pair by a second coupling transistor, a channel width of the first coupling transistor being different than a channel width of the second coupling transistor; and

a second plurality of static random access memory cells coupled to the power supply voltage terminal, a memory cell of the second plurality of static random access memory cells having a first storage node coupled to a first bit line of a second bit line pair by a third coupling transistor, and second storage node coupled to a second bit line of the second bit line pair by a fourth coupling transistor, a channel width of the third coupling transistor being substantially equal to a channel width of the fourth coupling transistor

13. The static random access memory array of claim 12, wherein the plurality of word lines are polysilicon word lines.

14. The static random access memory array of claim 12, wherein the power supply voltage terminal is coupled to ground potential.

15. The static random access memory array of claim 12, wherein both the first plurality of static random access memory cells and the second plurality of static random access memory cells are four transistor static random access memory cells having polysilicon load resistors and N-channel MOS transistors.

16. The static random access memory array of claim 12, wherein the memory cell of the first plurality of static random access memory cells comprises:

a first load element having a first terminal and a second terminal;

a second load element having a first terminal and a second terminal;

a first pull-down transistor having a first current electrode coupled to the second terminal of the first load element, a second current electrode coupled to the power supply voltage terminal, and a control electrode;

a second pull-down transistor having a first current electrode coupled to the second terminal of the second load element, a second current electrode coupled to the power supply voltage terminal, and a control electrode;

the first coupling transistor having a first current electrode coupled to the first current electrode of the second pull-down transistor, a control electrode coupled to one of the word lines, and a second current electrode coupled to the first bit line of the first bit line pair, the first coupling transistor having a first channel width; and

the second coupling transistor having a first current electrode coupled to the first current electrode of the first pull-down transistor, a control electrode coupled to the word line, and a second current electrode coupled to the second bit line of the second bit line pair, the second coupling transistor having a second channel width, the first channel width being less than the second channel width.