Semiconductor memory

• US 5,365,478 A
• Filed: 02/09/1994
• Issued: 11/15/1994
• Est. Priority Date: 05/13/1981
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Hitachi, Ltd.
• Inventors: Kawamoto, Hiroshi, Shimohigashi, Katsuhiro, Masuda, Hiroo, Ikuzaki, Kunihiko
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US08/193,896
• Time in Patent Office: 279 Days
• Field of Search: 365/189.01, 365/189.05, 365/186, 365/203, 365/205, 365/51, 365/210
• US Class Current: 365/210.14
• CPC Class Codes: G11C 11/409 Read-write [R-W] circuits
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 11/4097 Bit-line organisation, e.g. bit-line layout, folded bit lines
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/30 DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells

Abstract

A dynamic RAM integrated circuit of the one-element memory cell type is provided with a plurality of data lines, a sense amplifier, a plurality of word lines disposed in a manner to intersect with the data lines, and memory cells disposed at the points of intersection between the data lines and the word lines. The RAM includes a P-type semiconductor substrate and an N-type well region formed in the substrate. The memory cells are disposed within the well, and the sense amplifier, which is connected to the date lines, is constructed of a pair of N-channel MOSFETs formed in the semiconductor substrate and a pair of P-channel MOSFETs formed in the well region.

Claims

1. A semiconductor memory formed in a semiconductor integrated circuit comprising:

a pair of data lines disposed substantially parallel and adjacent to each other;

a word line arranged so as to intersect with both data lines of said pair of data lines;

a dummy line arranged so as to intersect with both data lines of said pair of data lines;

a memory cell coupled to said word line and to at least one data line of said pair of data lines at a cross point of said word line and said at least one data line;

a dummy cell coupled to said dummy word line and to at least one data line of said pair of data lines at a cross point of said dummy word line and said at least one data line;

amplifier means coupled to said pair of data lines for amplifying a potential difference between said data lines, and including first and second terminal which receive a first reference voltage and a second reference voltage, respectively, to operate said amplifier means;

precharging means for setting said pair of data lines at an intermediate potential between said first reference voltage and said second reference voltage; and

selecting means for selecting said word line and said dummy word line.

2. A semiconductor memory according to claim 1, wherein said dummy cell is selected by said selecting means when said memory cell is selected.

3. A semiconductor memory according to claim 2, wherein said amplifier means comprises first and second circuits;

wherein said first circuit includes a pair of crosscoupled N-channel MISFETs coupled to said pair of data lines for bringing about a differential amplification operation; and

wherein said second circuit includes a pair of cross-coupled P-channel MISFETs coupled to said pair of data lines for bringing about a differential amplification operation.

4. A semiconductor memory according to claim 3, wherein the differential amplification operation of said first circuit is started at a time different from the time when the differential amplification operation of said second circuit is started.

5. A semiconductor memory according to claim 3, wherein said first terminal is coupled to a source side of said first circuit and is supplied with said first reference voltage and wherein said second terminal is coupled to a source side of said second circuit and is supplied with said second reference voltage.

6. A semiconductor memory according to claim 5, wherein the differential amplification operation of said first circuit is started in response to said first reference voltage being supplied to said source side of said first circuit, and wherein the differential amplification operation of said second circuit is started in response to said second reference voltage being supplied to said source side of said second circuit.

7. A semiconductor memory according to claim 6, further comprising an N-channel MISFET coupled between said first terminal and said first reference voltage for controlling the differential amplification operation of said first circuit, and a P-channel MISFET coupled between said second terminal and said second reference voltage for controlling the differential amplification operation of said second circuit.

8. A semiconductor memory according to claim 7, wherein said dummy cell includes a series connection circuit comprised of first and second MISFETs.

9. A semiconductor memory according to claim 8, wherein said first and second MISFETs are P-channel MISFETs.

10. A semiconductor memory formed in a semiconductor integrated circuit comprising:

a pair of data lines;

a word line arranged so as to intersect with one data line of said pair of data lines;

a dummy word line arranged so as to intersect with the other data line of said pair of data lines;

a memory cell coupled to said word line and to said one data line of said pair of data lines;

a dummy cell coupled to said dummy word line and to said other data line of said pair of data lines;

amplifier means coupled to said pair of data lines for amplifying a potential difference between said data lines, and including first and second terminals which receive a first reference voltage and a second reference voltage, respectively, to operate said amplifier means;

precharging means for setting said pair of data lines at an intermediate potential between a first reference voltage and a second reference voltage; and

selecting means for selecting said word line and said dummy word line.

11. A semiconductor memory according to claim 10, wherein said dummy cell is selected by said selecting means when said memory cell is selected.

12. A semiconductor memory according to claim 11, wherein said amplifier means comprises first and second circuits;

wherein said first circuit includes a pair of crosscoupled N-channel MISFETs coupled to said pair of data lines for bringing about a differential amplification operation; and

wherein said second circuit includes a pair of cross-coupled P-channel MISFETs coupled to said pair of data lines for bringing about a differential amplification operation.

13. A semiconductor memory according to claim 12, wherein the differential amplification operation of said first circuit is started at a time different from the time when the differential amplification operation of said second circuit is started.

14. A semiconductor memory according to claim 12, wherein said first terminal is coupled to a source side of said first circuit and is supplied with said first reference voltage and wherein said second terminal is coupled to a source side of said second circuit and is supplied with said second reference voltage.

15. A semiconductor memory according to claim 14, wherein the differential amplification operation of said first circuit is started in response to said first reference voltage being supplied to said source side of said first circuit, and wherein the differential amplification operation of said second circuit is started in response to said second reference voltage being supplied to said source side of said second circuit.

16. A semiconductor memory according to claim 15, further comprising an N-channel MISFET coupled between said first terminal and said first reference voltage for controlling the differential amplification operation of said first circuit, and a P-channel MISFET coupled between said second terminal and said second reference voltage for controlling the differential amplification operation of said second circuit.

17. A semiconductor memory according to claim 16, wherein said dummy cell includes a series connection circuit comprised of first and second MISFETs.

18. A semiconductor memory according to claim 17, wherein said first and second MISFETs are P-channel MISFETs.

19. A semiconductor memory formed in a semiconductor integrated circuit comprising:

a pair of data lines disposed substantially parallel and adjacent to each other;

a word line arranged so as to intersect with both data lines of said pair of data lines;

a dummy word line arranged so as to intersect with both data lines of said pair of data lines;

a memory cell coupled to said word line and to at least one data line of said pair of data lines at a cross point of said word line and said at least one data line;

a dummy cell coupled to said dummy word line and to at least one data line of said pair of data lines at a cross point of said dummy word line and said at least one data line;

amplifier means coupled to said pair of data lines for amplifying a potential difference between said data lines, and including first and second terminals which receive a first reference voltage and a second reference voltage, respectively, to operate said amplifier means, said amplifier means comprising first and second circuits;

said first circuit including a pair of cross-coupled N-channel MISFETs coupled to said pair of data lines for bringing about a differential amplification operation; and

said second circuit including a pair of crosscoupled P-channel MISFETs coupled to said pair of data lines for bringing about a differential amplification operation;

precharging means for setting said pair of data lines at an intermediate potential between said first reference voltage and said second reference voltage; and

selecting means for selecting said word line and said dummy word line,

wherein the differential amplification operation of said first circuit is started at a time different from the time when the differential amplification operation of said second circuit is started.

20. A semiconductor memory according to claim 19, wherein said dummy cell is selected by said selecting means when said memory cell is selected.

21. A semiconductor memory according to claim 20, wherein said first terminal is coupled to a source side of said first circuit and is supplied with said first reference voltage, and wherein said second terminal is coupled to a source side of said second circuit and is supplied with said second reference voltage.

22. A semiconductor memory according to claim 21, wherein the differential amplification operation of said first circuit is started in response to said first reference voltage being supplied to said source side of said first circuit, and wherein the differential amplification operation of said second circuit is started in response to said second reference voltage being supplied to said source side of said second circuit.

23. A semiconductor memory according to claim 22, further comprising an N-channel MISFET coupled between said first terminal and said first reference voltage for controlling the differential amplification operation of said first circuit, and a P-channel MISFET coupled between said second terminal and said second reference voltage for controlling the differential amplification operation of said second circuit.

24. A semiconductor memory according to claim 23, wherein said dummy cell includes a series connection circuit comprised of first and secondMISFETs.

25. A semiconductor memory according to claim 24, wherein said first and secondMISFETs are P-channel MISFETs.