Error-correction encoding and decoding system

• US 5,365,530 A
• Filed: 05/12/1992
• Issued: 11/15/1994
• Est. Priority Date: 05/12/1992
• Status: Expired due to Fees

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Yoshida, Hideo
• Primary Examiner(s): Baker, Stephen M.
• Application Number:
  US07/881,533
• Time in Patent Office: 917 Days
• Field of Search: 371/37.4
• US Class Current: 714/755
• CPC Class Codes: H03M 13/29 combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
• CPC Class Codes: H03M 13/2903 Methods and arrangements specifically for encoding, e.g. parallel encoding of a plurality of constituent codes
• CPC Class Codes: H03M 13/2909 Product codes
• CPC Class Codes: H03M 13/2927 Decoding strategies

Abstract

The present invention provides an error-correction code encoding and decoding technique in which an information amount is variable in a block, and error-correction encoding in the block can be done efficiently without a substantial change in circuit configuration regardless of information amount. An encoder comprises a C1 encoding section for encoding an Ip information series, a C3 encoding section for encoding an Is information series, a control circuit for controlling the encoding sections based on an identification signal indicating whether the Is information series is contained, and a buffer memory. If an Is information series is contained, an area corresponding to the Is information series is deleted from check symbols of the Ip information series and replaced with coded data of the Is information series. A decoder decodes a received word thus encoded. This obviates superimposition-separation of C3 information, thereby realizing efficient error-correction encoding in a block, while maintaining an information amount of a block variable, without any change in circuit configuration based on information amount.

Claims

1. An error-correction code encoder, comprising:

a first encoding section for encoding an Ip information series of (k₁ ×

n₂) digits having k₁ digits in the first direction and n₂ digits in the second direction to coded data containing check symbols each having a length of (n₁ -k₁) digits in the first direction;

a second encoding section for encoding an Is information series of (r×

k₃) digits (where r≦

n₁ -k₁ and k₃ <

n₂) to data containing check symbols each having a length of (n₂ -k₃) digits in the second direction;

a buffer memory for storing the data and check symbols of both information series; and

an encoding control means for controlling said first and second encoding sections and said buffer memory to cause, when an Ip information series is input to said buffer memory, coded data encoded by said first encoding section to be output from said buffer memory, and, when both Ip information series and Is information series are input to said buffer memory, said first encoding section to encode the Ip information series, said second encoding section to encode the Is information series and said buffer memory to delete the check symbols of (r×

n₂) digits of the coded data encoded by said first encoding section and to output the remaining digits of the coded data encoded by said first encoding section and the data of (r×

n₂) digits of the coded data encoded by said second encoding section.

3. A decoder for decoding the data encoded by the encoder according to claim 1, comprising:

a buffer memory for storing a received word of (n₁ ×

n₂) digits sent from said encoder;

a first decoding section for decoding said received word for each k₁ -digit information data n₂ times to provide an Ip information series of (k₁ ×

n₂) digits;

a second decoding section for decoding said received word for each k₃ -digit information data r times to provide an Is information series of (r×

k₃) digits;

a decoding control means for controlling said buffer memory and first and second decoding sections to cause, when said received word input to said buffer memory is an Ip information series, said first decoding section to decode the Ip information series, and, when said received word input to said buffer memory contains both Ip information series and Is information series, said first decoding section to decode the Ip information series and said second decoding section to decode the Is information series.

4. A method for decoding the data encoded by the encoder according to claim 1, comprising the steps of:

(1) storing a received word of (n₁ ×

n₂) digits sent from said encoder;

(2) decoding said received work for each k₁ -digit information data n₂ time to provide an Ip information series of (k₁ ×

n₂) digits;

(3) decoding said received word for each k₃ -digit information data r times to provide an Is information series of (r×

k₃) digits;

causing, when said received word input to said buffer memory is an Ip information series, said step (2) to be carried out, and, when said received word input to said buffer memory contains both Ip information series and Is information series, said steps (2) and (3) to be carried out,

the r-digit data deleted in transmission being treated as eliminated digits whereby the eliminated portion is not corrected when the coded data of (k₁ ×

n₂) digits in said received word is decoded in the first direction.

2. An error-correction code encoding method, comprising the steps of:

encoding an Ip information series of (k₁ ×

n₂) digits having k₁ digits in the first direction and n₂ digits in the second direction to coded data containing check symbols each having a length of (n₁ -k₁) digits in the first direction;

encoding an Is information series of (r×

k₃) digits where r≦

n₁ -k₁ and k₃ <

n₂) to data containing check symbols each having a length of (n₂ -k₃) digits in the second direction;

storing the data and check symbols of both information series; and

causing, when an identification signal indicates that an Ip information series is input to said buffer memory, the coded data encoded by said first encoding section to be output from said buffer memory, and, when an identification signal indicates that both Ip information series and Is information series are input to said buffer memory, said first encoding section to encode the Ip information series, and the second encoding section to encode the Is information series and said buffer memory to output data including the coded data encoded by said first encoding section and the data of (r×

n₂) digits of the coded data encoded by said second encoding section,

check symbols of (r×

n₂) digits of the coded data encoded by said first encoder being not stored in said buffer memory when the Ip information series and the Is information series are encoded.

5. An error-correction code encoder, comprising:

a first encoding section for encoding an Ip information series to first coded data including first check symbols;

a second encoding section for encoding an Is information series to second coded data including second check symbols, wherein said second coded data includes fewer digits than said first check symbols; and

a buffer memory for storing said first and second coded data, such that a portion of said first check symbols is deleted and replaced by said second coded data.

6. The error-correction code encoder according to claim 5, further comprising encoding control means for controlling said first and second encoding sections and said buffer memory, such that when an Is information series is not input to said buffer memory, said portion of said first check symbols are not deleted.

7. The error-correction code encoder according to claim 6, wherein said encoding control means includes receiver means for receiving an identification signal which indicates when Is information is not input to said buffer memory.

8. An error-correction code encoding method, comprising the steps of:

encoding an Ip information series to first coded data including first check symbols;

encoding an Is information series to second coded data including second check symbols, wherein said second coded data includes fewer digits than said first check symbols;

deleting a portion of said first check symbols; and

replacing said deleted portion of said first check symbols with said second coded data.

9. The error-correction code encoding according to claim 8, further comprising the step of storing said first and second coded data in a buffer memory.

10. The error-correction code encoding method according to claim 9, further comprising the step of inhibiting said deleting and replacing steps when no Is information series is coded and no second coded data is input to said buffer memory.

11. The error-correction code encoding method according to claim 10, further comprising the step of receiving an identification signal which indicates when no Is information series is coded and no second coded data is input to said buffer memory.

12. A decoder for decoding encoded data including first data encoding an Ip information series and second data encoding an Is information series, a portion of check symbols of said first data being deleted and replaced by said second data in said encoded data when an Is information series is encoded, said decoder comprising:

a first decoding section for decoding a portion of said encoded data corresponding to said first data to provide an Ip information series; and

a second decoding section for decoding a portion of said encoded data corresponding to said second data to provide an Is information series.

13. A decoder according to claim 12, further comprising:

a decoder control means for controlling said first decoding section and said second decoding section such that when said encoded data includes said second data, said first decoding section treats said deleted portion of check symbols as eliminated digits and does not correct said deleted portion, and, when said encoded data does not include said second data, said first decoding section decodes all of said encoded data and said second decoding section does not decode said encoded data.

14. The decoder according to claim 13, wherein said decoder control means includes receiver means for receiving an identification signal which indicates whether said encoded data includes said second data.

15. A method for decoding encoded data including first data encoding an Ip information series and second data encoding an Is information series, a portion of check symbols of said first data being deleted and replaced by said second data in said encoded data when an Is information series is encoded, said method comprising the steps of:

decoding a portion of said encoded data corresponding to said first data to provide an Ip information series;

decoding a portion of said encoded data corresponding to said second data to provide an Is information series.

16. The method according to claim 15, wherein said first decoding step includes treating said deleted portion of check symbols as eliminated digits and not correcting said deleted portion, when said Is information series is encoded.

17. The decoder according to claim 15, wherein said decoding control means includes receiver means for receiving an identification signal which indicates whether said encoded data includes said second data.