Method of and apparatus for controlling modulation of digital signals in frequency-modulated transmissions

• US 5,365,546 A
• Filed: 07/22/1991
• Issued: 11/15/1994
• Est. Priority Date: 01/18/1990
• Status: Expired due to Term

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Norand Corporation (Baker Hughes Company)
• Inventors: Mahany, Ronald L., Koenck, Steven E., Frede, William W.
• Primary Examiner(s): Chin, Stephen
• Application Number:
  US07/735,128
• Time in Patent Office: 1,212 Days
• Field of Search: 375/7, 375/8, 375/9, 375/62, 375/76, 455/115, 455/116, 332/100, 332/117, 332/118, 307/356, 307/358, 307/530
• US Class Current: 375/223
• CPC Class Codes: B60R 11/02 for radio sets, television sets, telephones, or the like; Arrangement of controls thereof
• CPC Class Codes: B60R 11/0241 for telephones
• CPC Class Codes: G06F 1/1626 with a single-body enclosure integrating a flat display, e.g. Personal Digital Assistants [PDAs]
• CPC Class Codes: G06F 1/1632 External expansion units, e.g. docking stations
• CPC Class Codes: G06F 15/0225 User interface arrangements, e.g. keyboard, display; Interfaces to other computer systems
• CPC Class Codes: G06K 17/0022 arrangements or provisious for transferring data to distant stations, e.g. from a sensing device "transfer between computer elements G06F13/00 "; data-transmission H04L
• CPC Class Codes: G06K 7/10702 Particularities of propagating elements, e.g. lenses, mirrors G06K7/10831 takes precedence
• CPC Class Codes: G06K 7/10722 Photodetector array or CCD scanning
• CPC Class Codes: G06K 7/10841 Particularities of the light-sensitive elements semiconductor devices H01L
• CPC Class Codes: G06K 7/10851 Circuits for pulse shaping, amplifying, eliminating noise signals, checking the function of the sensing device basic electronic circuitry H03
• CPC Class Codes: G06K 7/10881 constructional details of hand-held scanners
• CPC Class Codes: G06K 7/1098 the scanning arrangement having a modular construction
• CPC Class Codes: G06K 7/12 using a selected wavelength, e.g. to sense red marks and ignore blue marks
• CPC Class Codes: G06Q 20/343 Cards including a counter
• CPC Class Codes: G07F 7/02 by keys or other credit registering devices
• CPC Class Codes: G07G 1/0045 with a code reader for reading of an identifying code of the article to be registered, e.g. barcode reader or radio-frequency identity [RFID] reader
• CPC Class Codes: H01Q 1/22 by structural association with other equipment or articles
• CPC Class Codes: H04B 1/1615 Switching on; Switching off, e.g. remotely battery saving circuits associated with selective call operation H04W52/00; details of power consumption reduction in a PLL, H03L7/0802, H03L7/14, H03L2207/08, H03L2207/18; muting amplifiers by gain control see H03G3/34
• CPC Class Codes: H04L 1/0002 by adapting the transmission rate
• CPC Class Codes: H04L 1/0025 Transmission of mode-switching indication
• CPC Class Codes: H04L 1/0029 : Reduction of the amount of signalling, e.g. retention of useful signalling or differential signalling power control H04W52/04
• CPC Class Codes: H04L 1/1671 : the supervisory signal being transmitted together with control information
• CPC Class Codes: H04L 1/1685 : the supervisory signal being transmitted in response to a specific request, e.g. to a polling signal
• CPC Class Codes: H04L 1/18 : Automatic repetition systems, e.g. Van Duuren systems
• CPC Class Codes: H04L 27/12 : Modulator circuits; Transmitter circuits
• CPC Class Codes: H04L 27/14 : Demodulator circuits; Receiver circuits
• CPC Class Codes: H04L 27/156 : with demodulation using temporal properties of the received signal, e.g. detecting pulse width
• CPC Class Codes: H04L 69/18 : Multiprotocol handlers, e.g. single devices capable of handling multiple protocols
• CPC Class Codes: H04L 69/32 : Architecture of open systems interconnection [OSI] 7-layer type protocol stacks, e.g. the interfaces between the data link level and the physical level
• CPC Class Codes: H04L 9/40 : Network security protocols
• CPC Class Codes: H04M 7/006 : Networks other than PSTN/ISDN providing telephone service, e.g. Voice over Internet Protocol (VoIP) , including next generation networks with a packet-switched transport layer H04L65/00 takes precedence; aspects not specific to the type of network H04M3/00; special services in those networks H04M3/42
• CPC Class Codes: H04W 52/028 : switching on or off only a part of the equipment circuit blocks
• CPC Class Codes: H04W 88/02 : Terminal devices
• CPC Class Codes: H04W 88/06 : adapted for operation in multiple networks or having at least two operational modes, e.g. multi-mode terminals
• CPC Class Codes: Y02D 30/70 : in wireless communication networks

Abstract

An interface device interacts between a digital data terminal and a frequency modulated analog transceiver module to control data flow between the digital data terminal and the transceiver module and to adapt the transceiver module to transmit digital data signals and to communicate messages containing digital signals to the digital data terminal. The interface circuit includes a digitally implemented signal shaping circuit which samples an analog quiescent state bias signal level of a voltage controlled oscillator circuit of the transceiver module. The signal shaping circuit samples and converts the sampled quiescent bias signal level to an equivalent digital data value. The digital equivalent value is increased by and decreased by a predetermined deviation value, thereby generating equivalent values of high and low modulation bias voltage levels. The interface device includes a programmable memory for storing a number of reference values which allow the interface device to be configured to normalize data signals and control sequences in accordance with operating characteristics of any one of a number of available transceiver modules. The stored reference values control timing sequences for initiating and shutting down a transmit cycle, for storing predetermined maximum deviation values for the modulation bias signal of transmitted data messages, and for demodulating received signals.

Claims

1. A method of controlling data flow between a digital data device and an analog communication device which includes a voltage controlled oscillator circuit, said method including receiving digital data messages, generating an analog signal modulated with said digital data messages and applying said modulated analog signal to the oscillator circuit of the analog communication device, said method further comprising:

storing a digitally coded value equivalent of a quiescent bias signal level which when applied to the oscillator circuit will cause the oscillator circuit to operate at a channel frequency;

generating a high and a low modulation analog signal level with respect to said stored digitally coded value equivalent of said quiescent bias signal level; and

applying to the oscillator circuit said analog signal modulated with said high and low modulated analog signal levels in accordance respectively with high and low data signals of said received digital data messages.

2. The method according to claim 1, wherein generating said high and a low modulation analog signal levels with respect to said stored digitally coded value equivalent of said quiescent bias signal level comprises reading said stored digitally coded value and converting said read digitally coded value to an analog center signal corresponding to said quiescent bias signal level, and adding to and subtracting from said analog center signal a predetermined voltage level, thereby forming said high and low modulation analog signal levels, and wherein applying to the oscillator circuit said modulated analog signal comprises selectively coupling one of said high and low modulation analog signal levels to the oscillator circuit in a sequence corresponding respectively to high and low digital data signals of said digital data messages.

3. The method according to claim 1, further comprising storing a plurality of digitally coded deviation values, reading at least one of said plurality of digitally coded deviation values as a selected deviation value representative of a predetermined deviation magnitude with respect to said one digitally coded value equivalent to the quiescent bias signal level, and wherein generating said high and low modulation analog signal levels comprises adding said selected deviation value to said one digitally coded value to generate a high deviation value and subtracting said selected deviation value from said one digitally coded value to generate a low deviation value.

4. The method according to claim 3, wherein generating said high and low modulation analog signal levels comprises converting said high deviation value and said low deviation value to respective high and low analog signal levels and applying said high and low analog signal levels to first and second sample and hold circuits respectively, and wherein applying to the oscillator circuit said modulated analog signal comprises selectively coupling one of said high and low modulation analog signal levels to the oscillator circuit in accordance with a sequence of high and low data signals in said digital data message.

5. The method according to claim 3, further comprising receiving a control signal indicative of a selected data rate of at least first and second data rates for receiving said digital data messages, reading a first of said plurality of digitally coded deviation values as said selected deviation value upon receipt of said control signal indicative of said first data rate and reading a second of said plurality of digitally coded values as said deviation value upon receipt of said control signal indicative of said second data rate.

6. The method according to claim 5, wherein generating said high and low analog modulation analog signal levels comprises converting said high deviation value and said low deviation value to respective high and low analog signal levels and applying said high and low modulation analog signal levels to first and second sample and hold circuits respectively, and wherein applying to the oscillator circuit said modulated analog signal comprises selectively assessing the first and second sample and hold circuits to provide a sequence of said high and low modulation analog signal levels to the oscillator circuit corresponding to a sequence of high and low data signals in said digital data message.

7. The method according to claim 1, wherein the analog communication device is an FM radio frequency transceiver module, said method including transmitting from the transceiver module modulated signals of a predetermined deviation from said channel frequency in response to said applied high and low modulated analog signal levels, and receiving signals representing data messages from remote transmitter stations and transferring said received data message signals to the digital data device includes decoding said received data message signals as signals of predetermined modulated signal strength with respect to a known DC bias signal component, comprising:

storing a plurality of digitally coded values as reference values of predetermined magnitude;

switching the transceiver module between a transmit mode for a first predetermined time period and applying said modulated analog signal to the oscillator circuit during said first predetermined time period, and switching the transceiver module at the end of said first predetermined time period to a receive mode during which period data received by the transceiver module are transferable as data messages to the digital data device;

converting said received data message signals into digital data signals; and

decoding one of the plurality of said digitally coded values as a receive disable reference value; and

generating a timed receive disable signal of a length corresponding to a magnitude of said decoded receive disable reference value for disabling said converting of said data message signals during a second predetermined time period following switching the transceiver module to said receive mode.

8. The method according to claim 7, further comprising routing said analog signal modulated with said high and low modulated analog signal levels corresponding to said digital message through a signal filter while the transceiver module is in said transmit mode, and routing the received digital data messages through the signal filter while the transceiver module is in said receive mode.

9. The method according to claim 7, further comprising amplifying said received data message signals, decoding a respective one of said stored digital coded reference values as a predetermined value of a received signal DC bias level of said received data message signals to be amplified, correcting for said received signal DC bias level to cancel the DC bias of said received data message signals prior to amplifying them, decoding a further one of said stored digitally coded reference values as a gain reference value, and amplifying said received data message signals in accordance with a gain corresponding to said decoded gain reference value chosen in accordance with an expected signal level of said received data message signals, thereby normalizing a signal output from the variable gain amplifier to a predetermined signal level.

10. The method according to claim 7, wherein said converting of said received data message signals into digital data signals comprises detecting peak signal levels of said received data message signals and generating an average signal level with respect thereto, determining signal amplitudes with respect to said average signal level, decoding a further of said plurality of stored digitally coded reference values indicative of a predetermined signal switching hysteresis characteristic, and adjusting a feedback characteristic of a comparator in accordance with said decoded signal switching hysteresis reference value for normalizing a switched output signal by the comparator, and driving a transistor switch with said normalized switched output, thereby generating said digital data signals in accordance with said received data messages.

11. A method of controlling data flow between a digital data device and an analog communication device which includes a voltage controlled oscillator circuit, said method including receiving digital data messages, generating an analog signal modulated with said digital data messages and applying said modulated analog signal to the oscillator circuit of the analog communication device, said method further comprising;

storing a value equivalent of a quiescent bias signal level which when applied to the oscillator circuit will cause the oscillator to operate at a channel frequency;

adding a deviation value to said stored quiescent bias signal level value to obtain a high modulation value;

subtracting said deviation value from said stored quiescent bias signal level value to obtain a low modulation value;

generating high and low modulation analog signal levels which correspond to said high and low modulation values, respectively; and

applying to the oscillator circuit said analog signal modulated with said high and low modulation signal levels in accordance with high and low digital data signals of said received digital messages.

12. An interface device for controlling data flow between a digital data device which includes a message source for providing data messages in digital format and an analog communication device which includes a voltage controlled oscillator circuit, said interface device including means for receiving said digital data messages and for generating and applying an analog signal modulated with said digital data messages to the oscillator circuit of the analog communication device, said interface device comprising;

means for storing a digitally coded quiescent bias value corresponding to a quiescent bias signal level which when applied to the oscillator circuit will cause the oscillator circuit to operate at a channel frequency;

means for generating a high and a low modulation analog signal level with respect to said stored digitally coded quiescent bias signal value; and

means for applying to the oscillator circuit said analog signal modulated with said high and low modulation analog signal levels in accordance respectively with high and low digital data signals of said received digital data messages.

13. The interface device according to claim 12, wherein said means for generating said high and low modulation analog signal levels with respect to said stored digitally coded quiescent bias signal value comprises means for reading and converting said stored digitally coded quiescent bias signal value to an analog center signal corresponding to said stored digitally coded quiescent bias signal value, and means for adding to and subtracting from said analog center signal a predetermined voltage level, thereby providing said high and low modulation analog signal levels, and wherein said means for applying to the oscillator circuit said modulated analog signal comprises means for selectively coupling one of said high and low modulation analog signal levels to the oscillator circuit in a sequence corresponding respectively to high and low digital data signals in said respective data messages.

14. The interface device according to claim 12, further comprising means for storing a plurality of digitally coded values, means for reading at least one of said digitally coded values as a deviation value representative of a predetermined deviation magnitude with respect to said stored digitally coded quiescent bias signal value, and wherein said means for generating said high and low modulation analog signal levels comprises means for adding said deviation value to said digitally coded quiescent bias signal value to generate a high deviation value and means for subtracting said deviation value from said digitally coded quiescent bias signal value to generate a low deviation value.

15. The interface device according to claim 14, further comprising at least one digital to analog converter circuit and at least first and second analog signal sample and hold circuits for retaining sampled analog signal levels, and wherein said means for generating said high and low modulation analog signal levels comprises means for converting said high deviation value and said low deviation value respectively to said high and low analog signal levels and for applying said high and low analog signal levels to said first and second analog sample and hold circuits respectively, and said means for applying to the oscillator circuit said modulated analog signal comprises means for selectively coupling one of said high and low analog signal levels to the oscillator circuit in accordance with a sequence of high and low digital data signals in said data messages.

16. The interface device according to claim 14, further comprising means for receiving a control signal indicative of a selected data rate of at least first and second data rates for receiving said data messages, means for reading a first of said plurality of digitally coded values as said deviation value upon receipt of said control signal indicative of said first data rate and for reading a second of said digitally coded values as said deviation value upon receipt of said control signal indicative of said second data rate.

17. The interface device according to claim 16, further comprising at least one digital to analog converter circuit and at least first and second analog signal sample and hold circuits for retaining sampled analog signal levels, and wherein said means for generating said high and low modulation analog signal levels comprises means for converting said high deviation value and said low deviation value respectively, to said high and low modulation analog signal levels and for applying said high and low modulation analog signal levels to said first and second sample and hold circuits respectively, and said means for applying to the oscillator circuit said modulated analog signal comprises means for selectively coupling said high and low analog signal levels to the oscillator circuit in accordance with said sequence of said high and low digital data signals of said data messages.

18. The interface device according to claim 12, wherein the analog communication device is an FM radio frequency transceiver module, the transceiver module being operable to transmit modulated signals of a predetermined deviation from said channel frequency in response to said applied high and low modulated analog signal levels and to receive signals representing data messages from remote transmitter stations for transfer of said data messages to said interface device as signals of a predetermined modulated signal strength with respect to a known DC bias signal component, said interface device further comprising:

means for storing a plurality of digitally coded values of a predetermined magnitude, said digitally coded values being reference values;

means for switching the transceiver module to a transmit mode for a first predetermined time period during which said means for applying said modulated analog signal to the oscillator circuit is activated, and at the end of said first predetermined time period to a receive mode during which period data received by the transceiver module are transferable as data messages to the digital data device;

means for converting signals representative of said data messages received from the transceiver module into digital data signals; and

means for decoding one of said plurality of digitally coded values to provide a receive disable reference value and for generating a timed receive disable signal of a length corresponding to said receive disable reference value for disabling said means for converting signals during a second predetermined time period following the switching of the transceiver module to said receive mode.

19. The interface device according to claim 18, further comprising a signal filter, and means for routing said analog signal modulated with said high and low modulation analog signal levels in accordance with said high and low digital data signals of said data messages through said signal filter while the transceiver module is in said transmit mode, and for routing said received digital data messages through said signal filter while the transceiver module is in said receive mode.

20. The interface device according to claim 18, further comprising a variable gain amplifier for amplifying the signals representing said data messages received from the transceiver module, means for decoding a respective one of said stored reference values as a predetermined value of a received signal DC bias level of the signals representing said received digital data message, and means for applying said decoded value of said received signal DC bias level to said variable gain amplifier to cancel said decoded value of said received signal DC bias level prior to amplifying said data message signals, and means for decoding a further one of said stored reference values as a gain reference value, means for applying said decoded gain reference value to said variable gain amplifier to modify the gain thereof in accordance with an expected signal level of said data message signals, thereby normalizing a signal output from said variable gain amplifier to a predetermined signal level.

21. The interface device according to claim 18, wherein said means for converting said signals representative of said data messages received from the transceiver module into digital data signals comprises means for detecting peak signal levels of said received data message signals and for generating an average signal level with respect thereto, and comparator means for comparing signal amplitudes with respect to said average signal level to provide a comparator output, said interface device further comprising means for decoding a further one of said stored digitally coded reference values indicative of a predetermined signal switching hysteresis characteristic, means for adjusting a feedback characteristic of said comparator means in accordance with said decoded signal switching hysteresis reference value, thereby normalizing said comparator output signal, a transistor switch having a gate coupled to receive said comparator output signal which drives said transistor switch for generating said digital data signals in accordance with said received digital data messages.

22. An interface device for controlling bidirectional data transfer between a digital data device and a frequency modulated transceiver module having a voltage controlled crystal oscillator circuit operable at a predetermined channel frequency in response to a quiescent voltage level applied to the oscillator circuit, said interface device comprising;

timing control means for controlling an initiation, a duration, and a shut down of a transmit cycle of the transceiver module in response to an external control signal indicative of the digital data device being ready to transmit data via the transceiver module;

means for storing a plurality of reference values including reference values representing digital equivalent values of timed signals for controlling said initiation, said duration and said shut down of said transmit cycle of the transceiver module; and

means for decoding selected ones of said stored reference values as timing reference values, for generating timed signals and for applying timed signals to said timing control means in accordance with said stored reference values to control a timing sequence responsive to ramp up and ramp down characteristics of the transceiver module.

23. The interface device according to claim 22, which comprises:

means for decoding at least one of said stored reference values indicative of a timed value with respect to said external control signal for sampling said quiescent voltage level corresponding to said channel frequency of the oscillator circuit at a predetermined timed before data are transmitted by the transceiver module;

means for generating a digital reference signal corresponding to said sampled quiescent voltage level;

means for applying a deviation reference value of said stored reference values to said generated digital reference signal for generating a high and a low deviation value;

means for converting said high and low deviation values to analog signal values corresponding respectively to high and low bias signal levels with respect to said sampled quiescent channel frequency voltage level; and

means for transferring a bias signal modulated with said high and low bias signal levels in accordance with a data message to be transmitted by the transceiver module.

24. Apparatus for generating a radio frequency modulated signal of a predetermined center frequency in accordance with binary data having a first data signal level and a second data signal level, said apparatus including a modulator with a node for establishing a quiescent bias voltage at the node for maintaining the accuracy of said predetermined center frequency in accordance with the amplitude of said quiescent bias voltage, said apparatus comprising:

(a) means coupled to the modulator for providing a path to the node to obtain a quiescent level signal whose amplitude is a measure of the amplitude of said quiescent bias voltage;

(b) means for generating a first modulator signal of an amplitude set less than that of said quiescent level signal by a predetermined amount to represent said first data signal level;

(c) means for generating a second modulator signal of an amplitude set greater than that of said quiescent level signal by said predetermined amount to represent said second data signal level; and

(d) means for applying said first modulator signal to the modulator when said binary data is at said first data signal level to cause a first frequency deviation of predetermined frequency shift in one direction from said center frequency and for applying said second modulator level signal to the modulator when said binary data is at said second data signal level to cause a second frequency deviation of said predetermined frequency shift in the other direction from said center frequency.

25. Apparatus according to claim 24, wherein there is included a DC modulating-signal-path having electrical characteristics for applying said first and second modulator signals to the modulator, whereby said quiescent level signal compensates for said characteristics of said DC modulating-signal-path so that said first and second frequency deviations are thereby maintained essentially symmetrical relative to said center frequency.

26. A method of operating a transmitter to generate a frequency modulated signal of a predetermined center frequency in accordance with binary data having first and second data signal levels, the transmitter providing at a node a quiescent bias voltage and having a modulator that is responsive to the quiescent bias voltage to maintain the accuracy of said predetermined center frequency, said method comprising the steps of:

(a) establishing a path to the node to obtain a quiescent level signal whose amplitude is a measure of the quiescent bias voltage;

(b) generating a first modulator level signal of an amplitude that is less than that of said quiescent level signal by a predetermined amount to represent said first data signal level;

(c) generating a second modulator level signal of an amplitude that is greater than that of said quiescent level signal by said predetermined amount to represent said second data signal level;

(d) applying said first modulator level signal to the modulator when said binary data is at said first data signal level to cause a first frequency deviation of predetermined frequency shift in one direction from said center frequency; and

(e) applying said second modulator level signal to the modulator when said binary data is at said second data signal level to cause a second frequency deviation of said predetermined frequency shift in the other direction from said center frequency.

27. A method according to claim 26, wherein said first and second modulator level signals are applied to the modulator via a DC modulating-signal-path having electrical characteristics, said quiescent level signal being compensated for said characteristics of the DC modulating-signal-path so that said first and second frequency deviations are thereby maintained essentially symmetrical relative to said center frequency.