Multi-processor having control over synchronization of processors in mind mode and method of operation

• US 5,371,896 A
• Filed: 05/17/1993
• Issued: 12/06/1994
• Est. Priority Date: 11/17/1989
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Guttag, Karl M., Balmer, Keith, Gove, Robert J., Ing-Simmons, Nicholas K.
• Primary Examiner(s): Bowler, Alyssa H.
• Assistant Examiner(s): Geckil, Mehmet
• Application Number:
  US08/062,867
• Time in Patent Office: 568 Days
• Field of Search: 395/200, 395/800, 395/375, 395/425, 395/650, 395/112, 395/162, 395/163, 395/550
• US Class Current: 712/20
• CPC Class Codes: G06F 15/8015 One dimensional arrays, e.g. rings, linear arrays, buses
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/3887 controlled by a single instruction for multiple data lanes [SIMD]

Abstract

There is disclosed a multiprocessor system arranged, in one embodiment, as an image and graphics processor. The processor is structured with several individual processors all having communication links to several memories without restriction. A crossbar switch serves to establish the processor memory links. The entire image processor, including the individual processors, the crossbar switch and the memories are contained on a single silicon chip. Each processor can operate to execute the same instruction at the same time (SIMD mode) or different instructions at the same time (MIMD mode).

Claims

1. A multi-processor system operable in either a single instruction multiple data (SIMD) mode, in a multiple instruction multiple data (MIMD) mode or in a synchronized multiple instruction multiple data (SMIMD) mode comprising:

a synchronization bus having a plurality of bus lines;

a SIMD/MIMD mode register storing therein an indication of either the single instruction multiple data (SIMD) mode or the multiple instruction multiple data (MIMD) mode;

a plurality of processors, each processor having

an instruction port from which each processor fetches a next instruction,

a synchronization register having a plurality of bits equal in number to the number of processors, each bit corresponding to a unique one of said plurality of processors, said synchronization register having stored therein an indication of which if any other of said processors are to be synchronized with said processor when in said multiple instruction multiple data (MIMD) mode thereby indicating said synchronized multiple instruction multiple data (SMIMD) mode,

an okay to synchronize circuit connected to a corresponding line of said synchronization bus for generating an okay to synchronize signal on said corresponding line of said synchronization bus when said processor is ready to fetch a next instruction,

a synchronization logic unit connected to said synchronization bus, said SIMD/MIMD mode register and said synchronization register for inhibiting the fetching the next instruction until each processor indicated as to be synchronized with said processor has transmitted said okay to synchronize signal via said synchronization bus when said SIMD/MIMD mode register indicates said multiple instruction multiple data (MIMD) mode and said synchronization register indicates said synchronized multiple instruction multiple data (SMIMD) mode, and

an execution unit for executing fetched instructions;

plurality of instruction memories, an instruction memory corresponding to each of said processors;

a switch matrix connected to said SIMD/MIMD mode register, to each of said plurality of processors and each of said instruction memories, said switch matrix including

a set of first links connected to said memories,

a second link having a plurality of sections equal number to the number of said processors, each section connected to said instruction port of a corresponding one said processors,

a plurality of buffers connected to said SIMD/MIMD mode register and disposed between adjacent sections of said second link forming a serial chain from a first processor to a last processor, each buffer connecting said adjacent sections of said second link when said SIMD/MIMD mode register indicates the single instruction multiple data (SIMD) mode, and splitting said adjacent sections of said second link when said SIMD/MIMD mode register indicates the multiple instruction multiple data (MIMD) mode, and

a plurality of crosspoints disposed at intersections between said first links and said sections of said second link, said crosspoints individually operating to connect said first links and said second link permitting said instruction port of a processor to receive an instruction from an instruction memory,

said plurality of crosspoints including a first crosspoint disposed at the intersection of said section of said second link connected to said instruction more of a predetermined first processor and said first link connected to said corresponding instruction memory which is always enabled to permit connection,

said plurality of crosspoints including a set of second crosspoints disposed at the intersection of each of said sections of said second link connected to said instruction port of processors other than said predetermined first processor and said respective first link connected to said corresponding instruction memories which are disabled to prohibit connection when said SIMD/MIMD register indicates the single instruction multiple data (SIMD) mode and enabled to permit connection when said SIMD/MIMD register indicates the multiple instruction multiple data (MIMD) mode.

2. The multi-processor system of claim 1, further comprising:

a communications bus permanently interconnecting all of said processors, said communication bus for coordinating change from the SIMD, MIMD and SMIMD modes.

3. The multi-processor system of claim 1, wherein:

each processor includes

a program counter having stored therein an address of a next instruction, and

an instruction fetch circuit for supplying to said instruction port said address stored in said program counter for fetching an instruction stored at said address; and

said switch matrix wherein

said buffers pass signals unidirectionally whereby when said buffers connect said adjacent sections of said second link in the single instruction multiple data (SIMD) mode only said program counter of a first processor in a serial chain of processors in the single instruction multiple data (SIMD) mode accesses its corresponding instruction memory.

4. The multi-processor system of claim 1, further comprising:

an external memory for storing instructions for each of said processors;

each instruction memory stores only a portion of the instructions for the corresponding processor; and

each processor further includes

a cache logic circuit connected to said SIMD/MIMD mode register and said program counter for determining if the instruction corresponding to the address stored in said program counter is stored in said corresponding instruction memory,

said cache logic circuit requesting the instruction corresponding to the address stored in said program counter from said external memory if the instruction is not stored in said corresponding instruction memory when said SIMD/MIMD register indicates said processor is in the multiple instruction multiple data (MIMD) mode,

said cache logic circuit of each processor not a first processor of a serial chain of processors in the single instruction multiple data (SIMD) mode being disabled, and

said cache logic circuit of a first processor of a serial chain of processors in the single instruction multiple data (SIMD) mode requesting the instruction corresponding to the address stored in said program counter from said external memory if the instruction is not stored in said corresponding instruction memory.

5. The multi-processor system of claim 1, wherein:

said SIMD/MIMD mode register stores therein an indication of either the single instruction multiple data (SIMD) mode or the multiple instruction multiple data (MIMD) mode for each of said plurality of processors;

said switch matrix wherein

said buffers connect adjacent sections of said second link in a serial chain from a first processor through to a last processor, each of said plurality of buffers connecting said adjacent sections of said second link only when said SIMD/MIMD mode register indicates the single instruction multiple data (SIMD) mode for a corresponding processor, and splitting said adjacent sections of said second link when said SIMD/MIMD mode register indicates the multiple instruction multiple data (MIMD) mode for the corresponding processor,

said second crosspoints being disabled to prohibit connection when said SIMD/MIMD register indicates the single instruction multiple data (SIMD) mode for a corresponding processor and enabled to permit connection when said SIMD/MIMD register indicates the multiple instruction multiple data (MIMD) mode for the corresponding processor.

6. The multi-processor system of claim 5, wherein:

each processor includes

a program counter having stored therein an address of a next instruction, and

an instruction fetch circuit for supplying to said instruction port said address stored in said program counter for fetching an instruction stored at said address; and

said switch matrix wherein

said buffers pass signals unidirectionally whereby when said buffers connect said adjacent sections of said second link in the single instruction multiple data (SIMD) mode only said program counter of the first processor in a serial chain accesses said its corresponding instruction memory.

7. The multi-processor system of claim 1, wherein:

each processor wherein said synchronization logic unit includes

a plurality of two input first NAND gates equal in number to the number of processors, each having an output, a first input connected to a line of said synchronization bus connected to said okay to synchronize unit of a corresponding processor and a second input line connected to a bit of said synchronization register corresponding to said corresponding processor, and

a second NAND gate having a plurality of inputs connected to said output of said plurality of first NAND gates and an output generating the output of said synchronization logic unit.

8. The multi-processor system of claim 1, wherein:

each processor wherein

said execution unit includes a first instruction responsive circuit for loading an instruction specified set of bits into said synchronization register in response to execution of a synchronization write instruction, whereby said synchronization write instruction specifies said indication, stored in said synchronization register, of which if any other of said processors are to be synchronized with said processor.

9. The multi-processor system of claim 1, wherein:

each processor further includes

a synchronization flag memory connected to said synchronization control logic having stored therein an indication of whether said processor is in the synchronized multiple instruction multiple data (SMIMD) mode or in the multiple instruction multiple data (MIMD) mode, and

wherein said synchronization logic unit is connected to said synchronization flag memory and

inhibits the fetching the next instruction until each processor indicated as to be synchronized with said processor has transmitted said okay to synchronize signal via said synchronization bus when said SIMD/MIMD register indicates said multiple instruction multiple data (MIMD) mode and said synchronization flag memory indicates said synchronized multiple instruction multiple data (SMIMD) mode, and

permits the fetching of the next instruction regardless of the status of said synchronization bus and said synchronization register when said synchronization flag memory indicates said multiple instruction multiple data (MIMD) mode.

10. The multi-processor system of claim 9, wherein:

each processor further includes

a two input NAND gate having a first input connected to said okay to synchronize circuit for receiving said okay to synchronize signal, a second input connected to said synchronization flag memory, and an output connected to said corresponding line of said synchronization bus,

whereby said okay to synchronize signal is transmitted to said synchronization bus whenever either (a) said okay to synchronize circuit generates said okay to synchronize signal and said synchronization flag memory indicates the synchronized multiple instruction multiple data (SMIMD) mode, or (b) said synchronization flag memory indicates the multiple instruction multiple data (MIMD) mode.

11. The multi-processor system of claim 9, wherein:

each processor wherein

said execution unit includes a second instruction responsive circuit for loading an indication of the synchronized mode into said synchronization flag memory in response to execution of a lock instruction, whereby said lock instruction begins the synchronized multiple instruction multiple data (SMIMD) mode.

12. The multi-processor system of claim 9, wherein:

each processor wherein

said execution unit includes a third instruction responsive circuit for loading an indication of the multiple instruction multiple data (MIMD) mode into said synchronization flag memory in response to execution of a unlock instruction, whereby said unlock instruction ends the synchronized multiple instruction multiple data (SMIMD) mode.

13. A multi-processor system operable in either a single instruction multiple data (SIMD) mode or in a synchronized multiple instruction multiple data (SMIMD) mode comprising:

a synchronization bus having a plurality of bus lines;

a SIMD/SMIMD mode register storing therein an indication of either the single instruction multiple data (SIMD) mode or the synchronized multiple instruction multiple data (SMIMD) mode;

a plurality of processors, each processor having

an instruction port from which each processor fetches a next instruction,

an okay to synchronize circuit connected to a corresponding line of said synchronization bus for generating an okay to synchronize signal on said corresponding line of said synchronization bus when said processor is ready to fetch a next instruction,

a synchronization logic unit connected to said synchronization bus and said SIMD/MIMD mode register for inhibiting the fetching the next instruction until each other processor has transmitted said okay to synchronize signal via said synchronization bus when in said synchronized multiple instruction multiple data (SMIMD) mode, and

an execution unit for executing fetched instructions;

a plurality of instruction memories, each instruction memory corresponding to each of said processors;

a switch matrix connected to said SIMD/SMIMD mode register, to each of said plurality of processors and each of said plurality of memories, said switch matrix including

a set of first links connected to said memories,

a second link having a plurality of sections equal in number to the number of said processors, each section connected to said instruction port of a corresponding one of said processors,

a plurality of buffers connected to said SIMD/MIMD mode register and disposed between adjacent sections of said second link forming a serial chain from a first processor to a last processor, each buffer connecting said adjacent sections of said second link when said SIMD/SMIMD mode register indicates the single instruction multiple data (SIMD) mode, and splitting said adjacent sections of said second link when said SIMD/SMIMD mode register indicates the synchronized multiple instruction multiple data (SMIMD) mode, and

a plurality of crosspoints disposed at intersections between said first links and said sections of said second link, said crosspoints individually operating to connect said first links and said second link permitting said instruction port of a processor to receive an instruction from an instruction memory,

said plurality of crosspoints including a first crosspoint disposed at the intersection of said section of said second link connected to said instruction port of a predetermined first processor and said first link connected to said corresponding instruction memory which is always enabled to permit connection,

said plurality of crosspoints including a set of second crosspoints connected to said SIMD/MIMD mode register and disposed at the intersection of said section of said second link connected to said instruction port of processors other than said predetermined first processor and said respective first link connected to said corresponding instruction memories which are disabled to prohibit connection when said SIMD/SMIMD register indicates the single instruction multiple data (SIMD) mode and enabled to permit connection when said SIMD/SMIMD register indicates the synchronized multiple instruction multiple data (SMIMD) mode.

14. The multi-processor system of claim 13, further comprising:

a communications bus permanently interconnecting all of said processors, said communication bus for coordinating change from the SIMD and SMIMD modes.

15. The multi-processor system of claim 13, wherein:

each processor includes

a program counter having stored therein an address of a next instruction, and

an instruction fetch circuit for supplying to said instruction port said address stored in said program counter for fetching an instruction stored at said address; and

said switch matrix wherein

said buffers pass signals unidirectionally whereby when said buffers connect said adjacent sections of said second link in the single instruction multiple data (SIMD) mode only said program counter of a first processor in a serial chain of processors in the single instruction multiple data (SIMD) mode accesses its corresponding instruction memory.

16. The multi-processor system of claim 13, further comprising:

an external memory for storing instructions for each of said processors;

each instruction memory stores only a portion of the instructions for the corresponding processor; and

each processor further includes

a cache logic circuit connected to said SIMD/MIMD mode register and said program counter for determining if the instruction corresponding to the address stored in said program counter is stored in said corresponding instruction memory,

said cache logic circuit requesting the instruction corresponding to the address stored in said program counter from said external memory if the instruction is not stored in said corresponding instruction memory when said SIMD/SMIMD register indicates said processor is in the synchronized multiple instruction multiple data (SMIMD) mode,

said cache logic circuit of each processor not a first processor of a serial chain of processors in the single instruction multiple data (SIMD) mode being disabled, and

said cache logic circuit of a first processor of a serial chain of processors in the single instruction multiple data (SIMD) mode requesting the instruction corresponding to the address stored in said program counter from said external memory if the instruction is not stored in said corresponding instruction memory.

17. The multi-processor system of claim 13, wherein:

said SIMD/SMIMD mode register stores therein an indication of either the single instruction multiple data (SIMD) mode or the synchronized multiple instruction multiple data (SMIMD) mode for each of said plurality of processors;

said switch matrix wherein

said buffers connect adjacent sections of said second link in a serial chain from a first processor through to a last processor, each of said plurality of buffers connecting said adjacent sections of said second link only when said SIMD/SMIMD mode register indicates the single instruction multiple data (SIMD) mode for a corresponding processor, and splitting said adjacent sections of said second link when said SIMD/SMIMD mode register indicates the synchronized multiple instruction multiple data (SMIMD) mode for the corresponding processor,

said second crosspoints being disabled to prohibit connection when said SIMD/SMIMD register indicates the single instruction multiple data (SIMD) mode for a corresponding processor and enabled to permit connection when said SIMD/SMIMD register indicates the synchronized multiple instruction multiple data (SMIMD) mode for the corresponding processor.

18. The multi-processor system of claim 17, wherein:

each processor includes

a program counter having stored therein an address of a next instruction, and

an instruction fetch circuit for supplying to said instruction port said address stored in said program counter for fetching an instruction stored at said address; and

said switch matrix wherein

said buffers pass signals unidirectionally whereby when said buffers connect said adjacent sections of said second link in the single instruction multiple data (SIMD) mode only said program counter of the first processor in a serial chain accesses said its corresponding instruction memory.

19. The multi-processor system of claim 13, wherein:

each processor wherein

said synchronization logic unit includes

a NAND gate having a plurality of inputs connected to respective lines of said synchronization bus and an output generating the output of said synchronization logic unit.

20. The method of operating a computer system having a plurality of processors each having a corresponding instruction memory, the method comprising the steps of:

storing a first indication of either a single instruction multiple data (SIMD) mode or a multiple instruction multiple data (MIMD) mode for each processor;

storing at each processor an indication of all other processors to which said processor is synchronized in a synchronized multiple instruction multiple data (SMIMD) mode;

storing at each processor a second indication of either a synchronized multiple instruction multiple data (SMIMD) mode or an unsynchronized multiple instruction multiple data (MIMD) mode;

generating at each processor a ready signal when said processor is ready to fetch an instruction;

connecting an instruction port of a first of the processors to a corresponding instruction memory;

connecting an instruction port of each processor in a serial chain of processors operating in the single instruction multiple data (SIMD) mode to an instruction memory corresponding to a first processor in the serial chain;

connecting an instruction port of each processor in the multiple instruction multiple data (MIMD) mode to a corresponding instruction memory;

inhibiting fetching an instruction at each processor in which said stored first indication indicates said multiple instruction multiple data (MIMD) mode and said second stored indication indicates said synchronized multiple instruction multiple data (SMIMD) mode until said processor receives said ready signal from all other processor or processors to which said processor is to be synchronized according to said stored indication; and

executing fetched instructions at each processor.

21. The method of claim 20, wherein each processor includes a cache logic circuit for requesting the instruction corresponding to the address stored in a program counter from an external memory if the instruction is not stored in the corresponding instruction memory, said method further comprising the step of:

disabling the cache logic circuit of each processor except the first processor in a serial chain of processors in the single instruction multiple data (SIMD) mode.

22. The method of claim 20, wherein:

said step of storing at each processor an indication of other processor or processors to which the processor is to be synchronized includes specifying the other processor or processors to which the processor is to be synchronized in response to execution of a first instruction by the processor.

23. The method of claim 20, wherein:

said step of specifying the other processor or processors to which said processor is to be synchronized includes specifying via a first instruction executed by said processor a subset of the other processors to which said processor is to be synchronized, said processor operating asynchronously with respect to other processors not in said subset.

24. The method of claim 20, wherein:

said step of specifying the other processor or processors to which said processor is to be synchronized includes specifying via a first instruction executed by said processor a plurality of groups of processors to be synchronized with respect to other processors in the same group and operating each group of processors asynchronously with respect to other groups of processors.

25. The method of claim 20, wherein:

said step of storing at each processor said second indication of either a synchronized multiple instruction multiple data (SMIMD) mode or an unsynchronized multiple instruction multiple data (MIMD) mode includes storing said second indication of the synchronized multiple instruction multiple data (SMIMD/mode in response to execution of a lock instruction by said processor.

26. The method of claim 20, wherein:

said step of storing at each processor said second indication of either a synchronized multiple instruction multiple data (SMIMD) mode or an unsynchronized multiple instruction multiple data (MIMD) mode includes storing said second indication of the unsynchronized multiple instruction multiple data (MIMD) mode in response to execution of an unlock instruction by said processor.

27. The method of claim 20, wherein:

said step of storing at each processor said second indication of either a synchronized multiple instruction multiple data (SMIMD) mode or an unsynchronized multiple instruction multiple data (MIMD) mode includes storing said second indication of the synchronized multiple instruction multiple data (SMIMD) mode in response to execution of a lock instruction by said processor and storing said second indication of the unsynchronized multiple instruction multiple data (MIMD) mode in response to execution of an unlock instruction by said processor.